Other Parts Discussed in Thread: ADS7953
NOTE: Using device ADS7953-Q1.
I have a few SPI related questions:
1. Does the ADS7953-Q1 operates in SPI Mode CPOL=0, CPHA=0? That is SDI is sampled on the rising edge, SDO is clocked out on the falling edge, and SCLK is LOW when CS_N asserts and negates?
2. In order to meet the Acquisition Time, I need to run additional SCLK cycles within the CS_N asserted frame, i.e. 23 cycles. Does the ADS7953-Q1 latch the SDI value after 16 SCLK's and ignore the remaining 7 SCLK cycles, or will this be a problem?
3. Similar to Question (2) above, after 16 SCLK cycles, what appears on the SDO output? The datasheet says SDO enters tre-state.