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ADS7953-Q1: SPI SCLK Cycles

Part Number: ADS7953-Q1
Other Parts Discussed in Thread: ADS7953

NOTE: Using device ADS7953-Q1.

I have a few SPI related questions:

1. Does the ADS7953-Q1 operates in SPI Mode CPOL=0, CPHA=0?  That is SDI is sampled on the rising edge, SDO is clocked out on the falling edge, and SCLK is LOW when CS_N asserts and negates?

2. In order to meet the Acquisition Time, I need to run additional SCLK cycles within the CS_N asserted frame, i.e. 23 cycles.  Does the ADS7953-Q1 latch the SDI value after 16 SCLK's and ignore the remaining 7 SCLK cycles, or will this be a problem?

3. Similar to Question (2) above, after 16 SCLK cycles, what appears on the SDO output?  The datasheet says SDO enters tre-state.

  • Hi Eric,

    1. Yes, you are correct on the SPI Mode.
    2. You can clock more than 16; the ADS7953 will latch the first 16 clocks and ignore the rest. However, for lowest noise, it would be best if the SCLK and SDI pins were held low during this period as this is the time when the input is acquired for the next conversion.
    3. After the 16th SCLK falling edge, the SDO will go Hi-Z (or floating). If your host reads the SDO pin at this time, it could read high or low depending on bus leakage.

    Regards, Keith N.
  • Hi Eric,

    If you have any other questions, please feel free to reply to this post.

    Regards,
    Keith N.