DAC38J84: Documentation Question: Do Manual Sections 7.3.2 and 7.3.3 Apply Consistent Meanings of "SerDes PLL Output Clock?"

Todd,

Section 7.3.2 and section 7.3.3 are strictly highlighting the SERDES PLL, which is different than the DAC PLL (7.4.12).

The SERDES PLL will basically take a reference clock (a divided down clock from the DAC PLL or directly from external clock, user selectable from register SERDES_REFERENCE_CLK_SELECT) See below registers

This reference clock can be divided down by serdes_refclk_div and also multiplied up through MPY value

The final required SERDES PLL rate depends on your line rate. We typically use full rate. For instance, with 10Gbps of SERDES line rate, your SERDES PLL need to be 2.5GHz.

-Kang

Hi Todd,

I understand your concern about the SERDES PLL. Our data converter team obtained the SERDES IP as a whole and integrated the IP with our data converter. Therefore, regarding your question #3, why does the SERDES receiver requires a separate PLL, it is because the entire SERDES is build on top of a single IP.

Our internal document of the SERDES IP only show 4 major components: power supply regulator for the SERDES PLL, phase frequency detector for the SERDES PLL, VCO circuit, and the MPY. There are no other detailed drawings besides the actual silicon design (which I have no access), and hence indicates a conventional PLL.

Regarding your questions:
1. The SERDES PLL consist of very simple elements and hence no diagram was shown. Only the traditional components were shown in our internal documents.
2. You are correct. The MPY automatically multiplies the PFD directly to the SERDES PLL output rate. This is done automatically. To get the PFD frequency for the SERDES PLL, you will need to divide the DAC PLL or external clock accordingly with the SERDES reference clock divider.
3. Actually, CDR only changes the sampling phase of the clock to ensure the serialized data stream are sampled at the optimal setup/hold time. The actual sampling clock still need to be generated by a clock source, and this is where the SERDES PLL is needed. The CDR is only a steering wheel, and the actual power still need to come from the engine (i.e. SERDES PLL).

-Kang

Hi Todd,

The JESD204B standard basically separates the physical layer away from the link layer and transport layer. The physical layer is the SERDES itself (i.e. the mouth and ears of communication), while the link and transport layer are responsible for the handshaking, link establishment, and data packing (i.e. the smarts or the brain of the communication).

The frame clock cycle or the multi-frame clock cycle are JESD204B standards to establish a common clock cycle in the link layer and transport layer so the data packets are basically processed at the same rate for both the FPGA and data converter. This sort of making the design common so the standards of different vendor can be compliant with each other.

the SERDES PLL output is strictly used to sample the serialized bit stream. It in theory should have different rate then the frame/multi-frame clock due to the 8b/10b encoding nature of the JESD204B standard.

The DACCLK cycle is simply the DAC sampling clock for the output core. This is effectively how fast the DAC can generate consecutive samples.

the JESD204B standard can be available to download on the JEDEC website. We also have various JESD204B trainings available on TI.com. You can do a quick search on these training materials.

thanks.

-Kang