This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

ADS7853: Concern with SPI interface

Part Number: ADS7853

Hi,

my customer is currently working on a design with ADS7853 and they have a concern.

First they set the configuration register for 16-bit mode, 2 data lines, etc Data: “1000_1010_0001_0000”

Clock frequency is 2.5 MHz for testing, started at 10 Mhz and that is what they are going to use in their product.

 

Green: CS_n

Digital 1: SDI

Blue: SCLK

Yellow: SDOA

Purple: SDOB

 

Next they init a readout of the configured values:

 

Then they read the configured values(here it is obvious that the output data is launched on the falling edge of sclk):

 

Finally they entered “runtime” where the values are read often.

 

Here you can see that the data is launched on the rising edge of the sclk. The datasheet states that the data should be launched on falling edge.

See page 42 and 43 in the datasheet. D11 should be put out on the second falling sclk after cs_n has gone low.

I can’t find anywhere in the datasheet that data should be launched on the rising edge, however on page 41 it looks like it in the diagram but the text and table says falling edge.

could you please help us here.

regards,

Stani

  • Hi Stani,

    It looks like I misread your question, I see what you mean about the apparent change in the launch edge of the SDO_A and SDO_B lines, let me look into this a little more for you.  In either 16 SCLK or 32 SCLK mode, both the SDI and SDO should be valid on the falling clock edge. 

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Hi Tom,

    thank for looking into this issue. I'll be waiting for your response.

    regards

    Stani 

  • In reply to Tom Hendrick:

    Hi Tom,
    sorry i'm coming back to you again on this. the customer is reaching out on a daily basis. i would appreciate if you could please find some time to look into this.

    thnaks.
  • In reply to Stani Bell Ngoufack Tchoufack89:

    Hi Stani,

    I actually am working on this but need input from the design side. What I see is that in 16-bit SDO mode, the conversion data launches with the rising edge, just as you see in the screen shots you sent. The data is still valid with the falling SCLK as defined in the datasheet, you just have significantly more setup time. I've asked the design team for an explanation for the behavior.

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Hi Tom,

    thanks for your reply. let us hope you get feedback from the design team.

    Regards,

    Stani

  • In reply to Stani Bell Ngoufack Tchoufack89:

    Hi Stani,

    I just talked with the design team and confirmed that in 16 clock mode, with dual SDO or single SDO, the output data is launched with the rising SCLK edge. Valid data in all cases though should still be with respect to the falling SCLK edge as I mentioned before. The datasheets will be updated to reflect this condition.

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Hi Tom,
    thanks for the reply. This answered their question.
    they have one last basic question: Will they get better accuracy if they design with a 14-bit adc and only use the highest 12 bits compared to a 12-bit adc?

    regards
    Stani
  • In reply to Stani Bell Ngoufack Tchoufack89:

    Hi Stani,

    Potentially - let's chat off line about this.

     

    Regards,

    Tom

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.