ADS124S06: To get a exact DRDY timing using DOUT/DRDY under previous DOUT output was "LOW"

Hi Onawa-san,

There are a couple of ways to determine if new conversion data are available by using DOUT/DRDY. If the output state of DOUT/DRDY is low there will be a short pulse when new conversion data are available. One method to detect this pulse is to use an edge triggered interrupt looking for a high to low transition on DOUT/DRDY. Another method for detecting the end of conversion is by polling the state of the DOUT/DRDY pin. When polling the pin for a state change, this small pulse could easily be missed, so in this case it is better to drive or force the DOUT/DRDY pin high after the conversion result is read.

This polling method is discussed in section 9.5.5 of the ADS124S06 datasheet. I will quote from this section here:
"When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives low, new data are available. If the
DOUT/DRDY line drives high, no new data are available. This procedure requires that DOUT/DRDY is forced high after reading each conversion result and before taking CS high. To make sure DOUT/DRDY is taken high, send a RREG command to read a register where the least significant bit is 1."

The only difficulty using this method is finding a register value where the LSB will be '1' consistently. Using the calibration registers (OFCAL and FSCAL) are not a good choice as these register can change with gain or recalibration. One good choice for the ADS124S06 is the ID register as the ID bits for the ADS124S06 has the LSB as '1'.

The process would be to read the last conversion result (either direct or by RDATA command) then issue a RREG command to read register 0. After the RREG the DOUT/DRDY will be forced high until the next end of conversion when DOUT/DRDY will go low.

Best regards,
Bob B