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DAC38J84: DAC38J84EVM + TSW14J10EVM + ZC706 issue

Part Number: DAC38J84
Other Parts Discussed in Thread: , LMK04828

Dear all

i am developing a FPGA based arbitrary waveform generator, have the system components  (DAC38J84EVM + TSW14J10EVM + ZC706).

i have made the connection and tried the use of HSDC pro +DAC3XJ8X GUI and configured and tested the generation of tone successfully.

Now my question is, i would like to use Vivado system design software suit for arbitrary waveform generation... can you provide example project based on my system ?

if its not available can you please help me developing the vivado based project ?

any help in this regard is highly appreciated 

thanks

  • Hi,
    you may go to the TSW14J10 web page on TI.com
    www.ti.com/.../TSW14J10EVM

    There is a link for firmware design file download
    www.ti.com/.../slac690

    -Kang
  • Hello

    thanks for your suggestions 

    i tried using TCL script to build the project in vivado TCL console,

    the problem is,i am currently using vivado 2018.2 and the given example on TI`s webpage support only 2016.1.

    kindly suggest some solution or update the firmware version for 2018.2.

    kindly reply

  • Hi,
    We will have to check if the firmware can be updated to the latest Vivado.
    -Kang
  • Hi,
    I was told that the firmware is only supported on older version of the Vivado.
    Our contacts at Xilinx do not want to provide new scripts that works on new versions.
    It is probably best that you contact your local Xilinx support to ask them for scripts for new versions.

    -Kang
  • Hi

    thank again for prompt reply.

    i have another question,

    keeping this in mind, i have the same set up of hardware so 

    is there any solution for generating customized/ arbitrary waveforms  on 4 DAC outputs of DAC38J84EVM..?

    i am able to generate single or double tone using HSDC pro.

    any help is appreciated

     

  • Hi Ravikant,

    Assuming you connect the DA38J84EVM to the TSW14J56EVM, you can load custom waveforms (.csv file) through our HSDC PRO software)

    You can generate your own patterns via Matlab for instance. You can create 4 columns of data, one column for each DAC.

    The format for the .csv data is signed 16bit integer (i.e. -32768 being most negative, and +32767 being most positive)

    The TSW14J56EVM user's guide discusses the memory depth supported on the DDR bus

    -Kang

  • Hi Kang

    thanks for your suggestions

    i am using HSDC PRO software to generate custom waveforms,

    now my question is how to set maximum sample rate of 2.5 GSPS at all four DAC  of DA38J84EVM .

    because i have to generate  80 MHz wave forms and i want to use maximum sampling capability of DA38J8EVM .

    please suggest the setting in DAC3XJ8X GUI to achieve 2.5 GSPS.

    Any help is appreciated.

    thanks

    Ravikant 

  • Hello Ravikant,

    Pretty much every mode in the DAC38J84 can support your need. You will need to look at the max bandwidth supported

    Afterwards, it is a matter of the lane rate and the number of lanes you have available on your FPGA. This is your application/system requirement, so we at TI cannot determine this for you.

    -Kang

  • Hello Kang 

    thanks for your suggestions again.

    i am trying to operate DAC38J84 at different frequency but i can only operate it in LMF-442 configuration,

    please suggest me the setting for LMF_841.

    i have tried doing it according to the table recommended by you but no response at output.

    for example my DAC3XJ8X setup is as follows, what else i need to do..?

    also, please suggest the LMK04828 clock output setup.

  • Ravikant,

    you are not giving us enough information to help you move forward. Please attach a ppt with the HSDC PRO screen shot and the steps you are going through to set up the device.

    Based on the screen shot above, the set up will just work.

    Also, it is best that you order the TSW14J56 EVM to check in parallel with your TSW14J10 setup.

    The setup of the TSW14J56EVM per described in the user's guide for DAC38J84 EVM is the most stable setup.

    -Kang
  • HSDC pro screenshots.pptxHi Kang.

    i have attached the ppt which includes screen shot of HSDC Pro setup. 

    Once again i am clarifying what i want to do,

    task: Generation of customized waveform (range of 80 MHz) at maximum possible sampling rate of DAC 38J84.

    so basically i need to know the setup for maximum sampling rate output setting.

  • DAC38J84_841_1228.8M.pptxDAC38J84_841_983.04M.pptxRavikant,

    Attached are two setup files to follow to get what you want. Since the -2 FPGA device on the ZC706 has serdes that are only rated to 10.3125Gbps, the 1228.8Msps case may not always work. It did work on my setup when I tried it though. The second file I have attached slows things down to 983.04Msps to stay within the spec of the device.

    Regards,

    Jim

  • Thanks Kang and Jim

    Now i am able to generate customized waveform .

    i have another issue i am generating .CSV file of 65536 samples in matlab. The array of samples looks like fine in matlab.

    but when i am loading the file to HSDC Pro,  and doing all the setup as usual i am still not getting output at DACs.

    could you please tell that .CSV file uploading in detail...in my case i am using MATLAB.

    note. I am able to generate test files at DAC output.

    thanks in advance

  • Ravikant,

    the loading of the .csv file instructions are in section 3.7.2 of the HSDC PRO user's guide
    www.ti.com/.../slwu087d.pdf

    There are example files that you can following in the default directory.

    -Kang
  • Dear Kang

    thanks for your support.

    i am able to generate customized patterns using my set up now, i have another issue..please suggest me some solution.

    due 16 bit DAC the number of samples are limited to 65536 so as length of waveform.

    i want to use this set up to generate different custom waveform together which are sequenced with each other.

    is their any method to generate such sequenced customized waveform like general arbitrary waveform generators..?

    any help will be appreciated..

    thanks in advance

    Ravikant

  • Basically i want to do.....Unique Real-time Sequencing that Links Multiple Waveform Files Creating Wave forms of longer length.
  • Ravikant,

    The 16-bit DAC resolution is the resolution of the DAC output swing and the granularity of the output swing (i.e. how fine we can represent the Y axis). It has nothing to do with the length of the pattern (i.e. X axis or time resolution). The length of the pattern is limited by your FPGA design. You will need to include DDR memory in your FPGA design to increase the length of the pattern being loaded onto the pattern generator. Using the on-chip memory of the FPGA sounds like are not sufficient for your design.

    -Kang

  • Hi kang
    thanks for help and suggestions
    Now please help to extend the memory as i am using ZC706 evaluation kit which has 1 GB DDR3 memory, please tell how can i add this memory to my FPGA design. do i need to change the Firmware..? or some setting in DAC38J84 GUI..?
    help is appreciated, its very urgent for me...
  • Hello Ravikant,

    Sorry, TI in general cannot help with additional development of FPGA firmware design for you. I would advise that you contact Xilinx directly for support.

    -Kang

  • hello Kang..

    thanks for suggestions

    i am seeking for help and suggestions from TI because i am following the set up settings of 

    (DAC38J84EVM + TSW14J10EVM + ZC706) as given in manual of TSW14J10EVM and HSDC pro user manual.

    Now i am in middle of something and just need to use the memory of ZC706 board in pattern generation so that i can upload pattern file of longer length in HSDC Pro.

    i request you again for any optional suggestion.

    thanks

  • Is it possible generate patterns of longer length using DAC28J84+TSW14J56.?

    i just want to confirm before buying it. The manual of TSW14J56 depicts it has quite well memory depth. 

  • Hello Ravikant,
    TI will not be able to be involved in FPGA work for our customer. You may contact our contract vendor for FPGA support. I believe they helped us on the TSW14J10 development. You will have to negotiate the contract yourself between you and Soliton.
    https://www.solitontech.com/

    -Kang