This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

AFE5809: Questions about AFE5809 CLOCKs

Genius 3485 points

Replies: 10

Views: 495

Part Number: AFE5809

Hi there,

We are using AFE5809 to develop an 128 channels high-end medical ultrasound machine. (We already used AFE5808A on our mid-end product, 64 channels). 

Although datasheet of 5809 recommends some clock gennerator and fan-out buffers such as LMK0480x and LMK0030x. We still hope to know more about how to design a ultra-low jitter and low-noise clock tree. Some questions as follow.

1. On page93-96, TI emphasised that clock source and buffer should be low phase noise and jitter for both ADC clock and CWx16 clocks. How to calculate those clock chain's jitter and select proper clock IC? My limited experiecne is, as ADC's aperture jitter is 450fs rms, so ADC clock tree's total rms jitter should be much less than 450fs. 

2. For now, we are investigating LMK04806, LMK00301and AD9528 of ADI, and found some difference in "Jitter". TI uses "Additive Jitter RMS" in LMK00301, and use "RMS jitter" in LMK04806. However, ADI uses both "Additive Time Jitter" and "Absolut Time Jitter". Are there STANDARD names and explanation for these different jitters?

3.For PCB layout and routing of 16pcs of AFE5809, we generally reuqire ADC clocks' traces to be equal-length with very small tolerance, and make it more difficult for routing. How should we select the proper length tolerance? ADC sample freq. is 50MHZ.

Thanks very much.

AD9528.pdf

  • Hi, How are you?
    We will reply to your message very soon.
    Thank you very much!
    Have a nice day!
    Best regards,
    Chen
  • In reply to Chen Kung:

    Hi Yi,
    How are you?
    Thank you for using AFE5809 device.
    Basically speaking, in order to obtain the best performance of the ADC from AFE5809 device,
    we no only need to know if the clock source has very high performance (i.e., low jitter noise)
    but also need to know the device's performance and application:
    such as what the input signal frequency is,
    what the thermal noise the device contains,
    and what the aperture jitter the device generates.

    Could you please let us know what the input signal frequency is?
    Is your input frequency running up to 65MHz (max input frequency of the AFE5809 device)?
    Or how lower than that frequency?

    Thank you very much!
    Have a nice day!

    Best regards,
    Chen
  • In reply to Chen Kung:

    Hi Chen

    1. Our appllicaiton is medical ultrasound machine.

    2. Input signal for AFE5809 is echo signals of ultrasound, generally 0~20MHZ AC small signals, Vp-p is in micro- to mili-volts range. This is common is ordinary medical ultrasound applicaitons.

    3. We set sample rate of AFE at 40MHZ or 50MHZ.

    I realize that we really care about clock design for this AFE. So if possible, you may help move this thread to CLOCK forum. Thanks.

  • In reply to yi xiao:

    Hi Yi,
    How are you?
    Yes, I have submitted your quesyoutions
    to the clock group HSDC-CTS group.
    (Also you can create a new forum to this group.)
    Hopefully they could replay to you soon.

    Thank you very much!

    Best regards,
    Chen
  • In reply to Chen Kung:

    Hi Yi,

    Hope this blog could help you.


    how-to-measure-additive-jitter-of-a-clock-buffer

    Best Regards,

    Shawn

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Shawn Han:

    Hi Yi,
    Could you highlight your questions had not been solved?

    Best Regards,
    Shawn

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Shawn Han:

    Hi Shawn,
    I read you link and it useful. However, pls help look into Q2 and Q3 . thanks!
  • In reply to yi xiao:

    Hi Yi,
    2, Jitter always is in "Time" domain. I looked through your attachment, which also use RMS jitter. So TI "Additive Jitter RMS" = ADI "Additive (RMS) Time Jitter", TI "RMS jitter" = ADI"Absolute (RMS)Time Jitter".

    3,
    "For PCB layout and routing of 16pcs of AFE5809, we generally reuqire ADC clocks' traces to be equal-length with very small tolerance, and make it more difficult for routing. How should we select the proper length tolerance? ADC sample freq. is 50MHZ."
    Sampling period = 1/50 MHz = 20 ns
    Suppose PCB FR4 Er =4.5, inner trace propagation delay is around 180 ps/inch.
    It is correct to keep ADC clocks' traces to be equal-length. The trace length difference tolerance depends on your sampling system synchronization accuracy requirements.

    Best Regards,
    Shawn

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Shawn Han:

    Hi Yi,

    How are you?

    Thanks for using AFE5809 device.

    For your question #3:

    Ideally the length matching for Analog Input Signals need to be totally matched

    from one channel to the other channel. This is necessary so that is why the datasheet did not

    mention any statement. However in the real application, it would need to depend on

    your requirement and application purpose.

    Please look at the following plot:

    When the Input Clock (CLKIN) starts rising-up

    and the first Input Signal can be Sampled at (for example) "Sample N" position.

    Then at the same time, the Second Input Signal can be Sampled at (not shown on this plot) "Sample N+1" position, for example.

    and so on.

     Therefore if all the Analog Input Signal trace length are not matched,

    then the sampled signals will cause different time-delay from one channel to the other channel

    as you can see.

    So please think in advance that

    how much % tolerance could be allowed by your system design.

    This is very important in term of your design tolerance.

    Thank you very much!

    Best regards,

    Chen

  • In reply to Chen Kung:

    Thanks for your help, Chen.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.