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DAC38RF83: Mirror output frequency with reduced level

Christoph Gollinger
Intellectual 255 points
Part Number: DAC38RF83

Hello,

we do sometimes observe mirror signals (mirrored to the NCO) on our DAC output.

Please see the attached screenshot.

After initialization and JESD synchronization the mirror signal either stays available or not until the next initialization.

The DAC38RF83 is set to Interpolation 18; LMFSHd = 44210; 2 TX; 9 GHz DACCLK.

What could be the reason for this?

Our assumption is that one lane might be delayed. Perhaps wrong lane buffer setting during initialization.

And therefore I- and Q­-data are delayed to each other.

How could this be double-checked? Is there a testmode in the DAC available to check the alignment of the lanes to each other?

Thank you in advance

Best regards

Christoph

  • 0
    TI__Genius 9695 points
    Hi Christoph,

    What is the effect on the image if you re-sync the NCO?
    The most likely cause is a relative delay between I and Q datapaths if the DAC is not SYNCed properly as per datasheet startup procedure in Figure 167.
    Also check JESD lane alarms reported in page1/2, address 0x64 to 0x67 for clues of JESD interface errors.

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Intellectual 255 points
    Hello Eben,

    thank you for your fast response. Following tests we did and additional information I can provide at the moment:

    NCO resync
    Unfortunately the NCO resync did not help to solve the mirror issue.
    The NCO resync has been done in following way.
    • Register 0x227 --> set bit 7 to select mem_spi_sync for NCOAB syncronization source (register value is 0x2282)
    • Register 0x228 --> toggle bit 1 LOW-HIGH-LOW to generate the SPI_SYNC signal (register values LOW=0x0000 – HIGH = 0x0002)
    This did not help. So it seems that the NCO is not the root cause.

    additional Test – route signal to other DUC Channel
    What i already would like to mention is, that the mirror signal ONLY appears on multi DUC Channel 2 (called DAC B in TI GUI) of the DAC.
    On multi DUC Channel 1 we were NOT able to get the mirror signal.
    Another test we did: On multi DUC Channel 1 we did “add adjacent DAC path AB” sample.
    Then the signal (including the mirror) of multi DUC Channel 2 is routed to multi DUC Channel 1.
    And then the mirror can be seen on multi DUC Channel 1 also.
    additional Test - subclass
    Aother thing we did test is to use subclass 0 instead of subclass 1. This also did not resolve the issue.

    Initialization
    We do not follow all steps of the suggested initialization of figure 167.
    The differences are:
    TRSTB is always pulled low by a pulldown, not exactly after the power supply rails are provided.
    The clock signal also is provided before the power is supplied to device.
    Do you think this could be a problem?

    JESD Alarm register
    We did check the alarm registers. They do not show any alarms.

    Best regards
    Christoph
  • 0 in reply to Christoph Gollinger
    TI__Genius 9695 points
    Hi Christoph,

    As we have discussed offline, the image may be due to the I and Q datapaths not synced correctly so the delays are different. Make sure SYSREF timing to device clock is fixed after every power cycle . Also, if you are AC coupling to the SYSREF interface, then use continuous SYSREF. If DC coupling, ensure the common mode is 500mV at the SYSREF interface.

    Thanks,
    Eben.