Hi Team,
In ADS54J20EVM board layout, we found that analog diff signals length match for intra pair is 0.5 Mils and for inter pair between I and Q channels is 0.5 mils .
Do we require this length match for analog differential lanes or 5 mils tolerance is ok? . Please guide us.
Please let us know what should be the length matching for Device clock and sysref clock.
Thanks and Regards,
Harshavardhan,K