Part Number: ADS54J20EVM
In ADS54J20EVM board layout, we found that analog diff signals length match for intra pair is 0.5 Mils and for inter pair between I and Q channels is 0.5 mils .
Do we require this length match for analog differential lanes or 5 mils tolerance is ok? . Please guide us.Please let us know what should be the length matching for Device clock and sysref clock.
Thanks and Regards,
You should try to route the analog inputs as close as possible (+/- 1mil) to minimize HD2, which is effected by any mismatch in phase between the inputs.
For the device clock and SYSREF, it is best to route these the same length to allow to meet setup and hold time (+/-5mils). If you are not sampling at max rate, this could be even higher. If you are using multiple converters, the lengths of these should all match. These do not have to match the pair going to your FPGA, but the pair used by the FPGA should match closely. See the attached document for more info.
1423.Multi-Device Synchronization of JESD204B Data Converters.pptx
0871.JESD204B Overview July_2018.pptx
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