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ADC12J4000EVM: ADC12J4000EVM problem with normal mode

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Replies: 3

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Part Number: ADC12J4000EVM

Hello Jim,

I have a problem with ADC12J4000EVM (Rev. E0) when digitizing analog signal applied to VIN.

Everything works fine when ADC is working in test modes (sending K28.5, RAMP and so on), the data received in the FPGA is perfect.
The problems start when trying to work in the normal mode.

My test conditions are as follows:
- Rf tone freq. applied to VIN is 480MHz
- Vector generator's power is set to -22dBm

The JESD outputs 20 samples at a time and approximately 4 of them look like a sine tone with amplitude +-150 (while full scale range is 2047).
All the other samples look like noise. When I change the signal's frequency to 240MHz, the data in the normally-looking samples reflects the change.
It doesn't seem like the data has nothing to do with the input signal but only 4 out of 20 samples don't look like noise.
What could be the problem?

When I increase input power from -22dBm to -20dBm, the FPGA's GTXs rxbyteisaligned status signals turn to 0.
How can the input signal's amplitude affect rxbyteisaligned signals?

As far as I understand, the default full scale range is 725mVpp into 100 Ohm, which translates to -1.82dBm.


  • Hi Dmitri
    Can you provide a chipscope or similar FPGA probe showing the octet data for each lane that you are seeing in Ramp test mode and in normal ADC data mode? Please include at least 2 Frames (16 octets) of data in the captures.
    Does your capture IP include logic to implement the alignment character monitoring and replacement required as part of the JESD204B standard? If not there will be unexpected characters at the end of some frames that your IP may interpret incorrectly, causing the rxbyteisaligned status errors you see.
    Jim B
  • In reply to Jim Brinkhurst1:

    Hello Jim,

    I use standard Xilinx JESD204B core (JESD_PHY + JESD_RX combined in one core). So th ebyte alignment is supposed to be done inside the Xilinx's IP core.

    gtX_rxbyteisaligned_out signals are status flags from the JESD_PHY core.

    Here is what I get:

    I) RAMP test mode

    JESD_PHY status signals gt[0..7]_rxbyteisaligned_out are all HIGH.

    JESD Ip core outputs:


    II) NORMAL Mode (Vector generator output frequency = 497MHz, two power levels frist -23dBm then -2dBm)

    JESD Ip core outputs:


    DEMAPPER outputs (signal level on Vector generator is -23dBm):


    All status signals on GTX outputs (JESD_PHY ip core) are HIGH.
    Some signals do look line a sine.

    Then I increase signal power to -2dBm

    The signals proportionally increased in amplitude:

    However the JESD_PHY (GTX statuses) are all LOW:




    Thanks in advance,



  • In reply to Dmitri:

    Hi Dmitri have you made any progress on this issue?
    You could try another test using the ADC in test pattern mode.
    This older thread has configuration files you can load using the ADC12J4000 EVM GUI Low Level View tab.
    One will Enable the ADC Test Pattern Mode and the other file will disable it. The older post also has some information on debugging the formatting that may be helpful.
    Best regards,
    Jim B

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