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ADC12J4000EVM: ADC12J4000EVM problem with normal mode

Dmitri
Prodigy 235 points
Part Number: ADC12J4000EVM
Other Parts Discussed in Thread: ADC12J4000

Hello Jim,

I have a problem with ADC12J4000EVM (Rev. E0) when digitizing analog signal applied to VIN.

Everything works fine when ADC is working in test modes (sending K28.5, RAMP and so on), the data received in the FPGA is perfect.
The problems start when trying to work in the normal mode.

My test conditions are as follows:
- Rf tone freq. applied to VIN is 480MHz
- Vector generator's power is set to -22dBm

The JESD outputs 20 samples at a time and approximately 4 of them look like a sine tone with amplitude +-150 (while full scale range is 2047).
All the other samples look like noise. When I change the signal's frequency to 240MHz, the data in the normally-looking samples reflects the change.
It doesn't seem like the data has nothing to do with the input signal but only 4 out of 20 samples don't look like noise.
What could be the problem?

When I increase input power from -22dBm to -20dBm, the FPGA's GTXs rxbyteisaligned status signals turn to 0.
How can the input signal's amplitude affect rxbyteisaligned signals?

As far as I understand, the default full scale range is 725mVpp into 100 Ohm, which translates to -1.82dBm.


Regards,
Dmitri.

  • 0
    TI__Mastermind 43870 points
    Hi Dmitri
    Can you provide a chipscope or similar FPGA probe showing the octet data for each lane that you are seeing in Ramp test mode and in normal ADC data mode? Please include at least 2 Frames (16 octets) of data in the captures.
    Does your capture IP include logic to implement the alignment character monitoring and replacement required as part of the JESD204B standard? If not there will be unexpected characters at the end of some frames that your IP may interpret incorrectly, causing the rxbyteisaligned status errors you see.
    Thanks,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 235 points

    Hello Jim,

    I use standard Xilinx JESD204B core (JESD_PHY + JESD_RX combined in one core). So th ebyte alignment is supposed to be done inside the Xilinx's IP core.

    gtX_rxbyteisaligned_out signals are status flags from the JESD_PHY core.

    Here is what I get:

    I) RAMP test mode

    JESD_PHY status signals gt[0..7]_rxbyteisaligned_out are all HIGH.

    JESD Ip core outputs:

    4f4e4d4c4f4e4d4c4f4e4d4c4f4e4d4c4f4e4d4c4f4e4d4c4f4e4d4c4f4e4d4c
    5352515053525150535251505352515053525150535251505352515053525150
    5756555457565554575655545756555457565554575655545756555457565554
    5b5a59585b5a59585b5a59585b5a59585b5a59585b5a59585b5a59585b5a5958
    5f5e5d5c5f5e5d5c5f5e5d5c5f5e5d5c5f5e5d5c5f5e5d5c5f5e5d5c5f5e5d5c
    6362616063626160636261606362616063626160636261606362616063626160
    6766656467666564676665646766656467666564676665646766656467666564
    6b6a69686b6a69686b6a69686b6a69686b6a69686b6a69686b6a69686b6a6968
    6f6e6d6c6f6e6d6c6f6e6d6c6f6e6d6c6f6e6d6c6f6e6d6c6f6e6d6c6f6e6d6c
    7372717073727170737271707372717073727170737271707372717073727170
    7776757477767574777675747776757477767574777675747776757477767574
    7b7a79787b7a79787b7a79787b7a79787b7a79787b7a79787b7a79787b7a7978
    7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c

    II) NORMAL Mode (Vector generator output frequency = 497MHz, two power levels frist -23dBm then -2dBm)

    JESD Ip core outputs:
    80075970a001e63f80fa84efe0f6705fc0f8babf90ff2f7010067fd090087cf0
    078cc0080870c004030650fdfc9ccff7f76c2ff7f79aaffcfd05700304683008
    40025490e0078d40b0076290b002fb7f80fb916f10f76aaf50f8ac9f30fe1580
    f9c10fff00363006068590080877a005041d70fefdad4ff8f76abff6f78b6ffb
    a0f6776f40fad12f000144c0100786a010086ea0500410e0c0fc9eff80f76e3f
    fa881ff7f76c2ff8f8b30ffefe1cb004057d9008088260060530e0ffffbf5ff9
    1001e2bf50fa800fc0f66f8f60f9bbbf30002ff0600681b0a0087ee0c0041d00


     

    DEMAPPER outputs (signal level on Vector generator is -23dBm):


     

    All status signals on GTX outputs (JESD_PHY ip core) are HIGH.
    Some signals do look line a sine.

    Then I increase signal power to -2dBm

    The signals proportionally increased in amplitude:

    However the JESD_PHY (GTX statuses) are all LOW:

     

     

     

    Thanks in advance,

    -Dmitri.

     

  • 0 in reply to Dmitri
    TI__Mastermind 43870 points
    Hi Dmitri have you made any progress on this issue?
    You could try another test using the ADC in test pattern mode.
    This older thread has configuration files you can load using the ADC12J4000 EVM GUI Low Level View tab.
    e2e.ti.com/.../2731337
    One will Enable the ADC Test Pattern Mode and the other file will disable it. The older post also has some information on debugging the formatting that may be helpful.
    Best regards,
    Jim B