Can someone clarify the symmetry spec for the CLKOUTP/CLKOUTM clock output. I see some reference to the clock in 6.10 but I am unclear if the typical duty cycle listed for the LVDS bit clock listed as 52% should be my design target.
I am driving the converter's input clock at 200MHz. Should I expect the output clock to be nominally 50%/50% with a variation up to 52%/48% or should I use 52%/48% as the typical symmetry. If this is the case then the clock high period would be 2.6ns and the clock low period would be 2.4ns. Is this correct?
Thanks,
Craig
