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ADS8885: Troubleshooting 3-Wire Digital Interface

Part Number: ADS8885
Other Parts Discussed in Thread: SN6501, LM7705, THS4521

Hello,

I am working on a data acquisition block employing the ADS8885 differential A/D converter. I am having trouble retrieving data from the converter through the 3-wire digital interface. For simplicity, I am not using the busy indicator function. Pages 5 and 21 of the data-sheet specify the protocol.

I am able to fetch the first N bits of the conversion data provided those bits are 0s. After the first 1 is output on DOUT, however, the ADS8885 output buffer appears to reset and subsequent clock edges generate a repeating sequence of bits. The oscilloscope trace below shows SCLK and DOUT. DOUT erroneously changes from HIGH to LOW before the 3rd falling clock edge. The received 18-bit data sequence is below:

001001001001001001

By lowering the differential input voltage, I am able to obtain other sequences, but they follow the same erroneous pattern:

000100010001000100

000010000100001000

000001000001000001

The relevant portion of the schematic and board I'm working with appear below. Do you have suggestions for troubleshooting this issue?

Thank you!

Wesley Hileman

============

Scope Trace: SCLK (Yellow, 1V/division) and DOUT (Pink, 1V/division). Horizontal 500ns/division. The falling edge of CONVST occurs immediately before the first falling edge of DOUT. CONVST remains LOW for the remainder of the scope trace duration.

Schematic (Digital Portion)

PCB (boxed zone corresponds to schematic):

  • Hello Wes,

    This could be power supply noise related or a timing issue.

    1. Replace L3 with a 0ohm jumper to reduce possible ringing on DVDD pin.
    2. Verify AVDD and DVDD are 3.3V.
    3. Verify VREF is between 2.5V and 5V.
    4. Verify AINP and AINM are between 0V and VREF.
    5. Confirm CONVST is held high for at least 1.3uS to allow the conversion to complete.
    6. If possible, capture a screen shot of one full frame (conversion) with CONVST, SCLK, and DOUT, similar to Figure 1 in the datasheet.

    The bypass capacitors are not in an ideal location; if none of the above help, you may want to add a 0.1uF cap directly between pin 2 (AVDD) and pin 5 (GND), and another 0.1uF cap between pin 10 (DVDD) and pin 5 (GND).

    Regards,
    Keith N.
    Precision ADC Applications
  • Hello Keith, 

    Thank you for the suggestions, they've proved helpful. I've measured AVDD and DVDD as 3.3V, VREF as 4.5V, AINP as 3.0V, and AINM as 2.6V relative to the analog ground plane. During each SPI transaction, ringing on AVDD/DVDD is not visible on the scope relative to analog ground. I bypassed L3 with a 0Ohm jumper, but the issue persists. I plan to add the 0.1uF caps between AVDD/DVDD and GND per your recommendation.

    Here's a scope trace showing a 3-wire transaction with CONVST, SCLK, and DOUT (without busy indicator):
    (3V/division vertical, 3.2us/division horizontal)

    I also attempted a 3-wire transaction using the busy indicator function. The start of the transaction appears in the trace below:
    (3V/division vertical, 1.3us/division horizontal)

    Here's a notion based on this trace:

    After the pulse on CONVST, a conversion starts and DOUT goes to 3-state and begins to pull up. The conversion completes and DOUT drives low. Falling SCLK edges begin to clock out the conversion data. However, another conversion appears to start when DOUT drives high for the first time. DOUT goes to 3-state again, but remains high due to the pull up. The conversion completes before the next falling SCLK edge, and DOUT drives low, violating the protocol. 

    I suspect capacitive coupling between the DOUT and CONVST pins may induce a pulse on CONVST when DOUT drives high, starting another conversion before the remaining data is clocked out (the CONVST and DOUT pins are adjacent on the ADS8885 package). In the trace, pulses are visible on CONVST when DOUT drives high.

    =====

    Thank you for your help. I greatly appreciate the support provided by TI.

    Best regards,
    Wes

     

  • Hi Wes,

    I think you are on the right path. It appears that noise is causing the part to start another conversion. You could try adding a small 10-100pF cap on the CONVST pin, as well as adding the 0.1uF caps on the AVDD and DVDD pins to ground.

    You may also want to change the part, just to eliminate a possible damaged device.

    Good luck.
    Regards,
    Keith
  • Hi Keith,

    I added the 0.1uF caps to the DVDD and AVDD pins and a 47pF cap to the CONVST pin. The cap on the CONVST pin appeared to prevent the erroneous conversions. I had to add another 47pF cap the the SCLK pin, as a similar issue occurred: each rising edge of DOUT coupled a pulse into SCLK, clocking out an additional bit. To reduce ringing, I placed 499 Ohm resistors in series with the SCLK and CONVST lines.

    I'm having some issues with stability of the digital output: of the 18 bits, only 8 remain constant for a DC input. I think this is a separate issue, and I'll plan to ask a separate question if I'm not able to solve it.

    Thanks,
    Wes
  • Hi Wes,

    The noise getting into the conversion results could be getting in on either the input or the reference. A quick check would be to short the input pins of the ADC to ground.

    The design seems overly sensitive to noise on the digital inputs. Adding the RC is typically not needed. Looking at your board layout, it looks like you separated the ground plane (I assume between analog and digital). Where on your board do the two grounds connect together? There should be a low impedance connection between the two planes directly underneath the ADC, otherwise, the digital return currents could be forced to flow through sensitive areas of the analog circuitry, such as the reference.

    Looking at your board, it looks like you have a good placement of the power, analog signal, and digital sections. You probably do not need a ground split at all (we typically try to design the EVM boards with a solid ground plane), but at a minimum, there should be a solid connection at the ADC.

    Regards,
    Keith
  • Hi Keith,

    Here's an image of the bottom copper layer showing the separation of the analog and digital grounds:

    The rightmost section is digital ground, and analog ground is adjacent. They connect at the 12V supply input near the top right corner of the board. The A/D converter is above the bottom right corner of analog ground.

    As you suggested, I'm thinking this layout causes the digital return currents to flow under the analog reference circuitry, introducing noise into the conversions. I'm going to short the AINP and AINM pins to ground to verify the source of the noise. To test for improvement, I may try to create a low impedance connection between the analog and digital grounds near the A/D converter.

    Thanks for your support.

    Wes

  • Hi Keith,

    When I shorted the ADC inputs (pins 3 and 4) to ground (pin 5), I obtained 0x00000 samples consistently. When I left the ADC inputs connected and shorted the differential inputs to the system, the noise in the samples remained. I paralleled a 10uF ceramic cap across the ADC inputs, reducing the input filter's -3dB bandwidth from about 800kHz to 800Hz. This significantly lowered the noise in the samples; for a DC input, the standard deviation was about 2 ADC units. I also tried creating a low impedance connection between the analog and digital ground planes near the ADC, but I could not notice an effect on the noise in the samples.

    Based on these results, I suspect most of the noise is coming in through the ADC input. The design includes a LM7705 switched-capacitor bias generator and a SN6501 push-pull driver that may contribute to the noise. Here's the full schematic for reference:

    Best regards,
    Wes

  • Hi Wes,

    The ground plane layout will result in high speed digital currents flowing through the reference circuit. This will have some impact on the overall noise in your system. Since you added an RC on the SCLK and CONVST pins to get the communications working, this should also help with noise coupling into the reference.

    I suggest working your way back through your signal chain to track down where the noise is getting in (it could be in multiple places).

    Start by connecting VN2/VP2 in your schematic to ground to isolate the THS4521+ADS8885 section of the circuit. If you have significant noise at this point, take a look at your power supply connections. (Make sure you are using a quiet lab supply feeding the input of the uA78M05.) You can also try reducing the resistor values by a factor of 2x (R2, R7, R9, R14). This will help reduce the effects of stray capacitance at the inputs of the THS4521 to the ground/power planes.

    Also, since the SN6501 is running from the same supply, I suggest disabling this section as well, just to eliminate it as a possible noise source. If this makes a significant difference, you may need to add additional capacitance on the +5VA supply, or use a different regulator.

    Regards,
    Keith
  • Hi Keith,

    Thank you for your help. I have the system working well enough for most of our uses, and I plan to continue to make improvements based on your suggestions.

    All the best,
    Wes