Other Parts Discussed in Thread: SN6501, LM7705, THS4521
Hello,
I am working on a data acquisition block employing the ADS8885 differential A/D converter. I am having trouble retrieving data from the converter through the 3-wire digital interface. For simplicity, I am not using the busy indicator function. Pages 5 and 21 of the data-sheet specify the protocol.
I am able to fetch the first N bits of the conversion data provided those bits are 0s. After the first 1 is output on DOUT, however, the ADS8885 output buffer appears to reset and subsequent clock edges generate a repeating sequence of bits. The oscilloscope trace below shows SCLK and DOUT. DOUT erroneously changes from HIGH to LOW before the 3rd falling clock edge. The received 18-bit data sequence is below:
001001001001001001
By lowering the differential input voltage, I am able to obtain other sequences, but they follow the same erroneous pattern:
000100010001000100
000010000100001000
000001000001000001
The relevant portion of the schematic and board I'm working with appear below. Do you have suggestions for troubleshooting this issue?
Thank you!
Wesley Hileman
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Scope Trace: SCLK (Yellow, 1V/division) and DOUT (Pink, 1V/division). Horizontal 500ns/division. The falling edge of CONVST occurs immediately before the first falling edge of DOUT. CONVST remains LOW for the remainder of the scope trace duration.
Schematic (Digital Portion)
PCB (boxed zone corresponds to schematic):