ADC32RF45: Bit errors in samples received by Xilinx JESD core

Shawn Bish

Part Number: ADC32RF45

I have a custom PCB with the ADC32RF45 connected to a Xilinx Kintex Ultrascale. I'm seeing errors in samples received in the FPGA over the JESD link. I'm looking for support from TI to help me debug this issue.

I'm uploading two files. The PDF contains a detailed description of the issue I'm having. The shell script contains my ADC configuration.

Thank you.

adc_issue.pdf

ti-adc32rf45-init.txt

#!/bin/bash
#
# Manually created using ADC32RFx_12bit_LMFS_82820.cfg.
#
# SYSREF must be on before writing to adc registers and can be shut off after
# completing ADC register writes.

APP=adc32rf45-test
DEV=/dev/spi.ti-adc32rf

# addressing:
# - r/w', m, p, ch, a11, ... , a0
#
# general registers:
# - analog:  m = 0, p = 0
# - digital: m = 1, p = 0
#
# analog pages:
# - *some* general registers
# - master page
# - adc page
#
# digital pages:
# - *some* general registers
# - selected by writing to 0x4002, 0x4003, 0x4004
#

########### SCB:  Step 1 (power on)            

########### SCB:  Step 2 in ADC spec table 103 (provide SYSREF) 
# turn on continunous sysref
cird /dev/spi.macb-dsbfpga << EOF
adc disable 
adc sysref mode cont
adc sysref enable
adc sysref status
adc enable
quit
EOF

########### SCB:  Step 3 (Reset pulse on ADC pin 48) ###########
br-ti-adc32rf-reset.sh

########### SCB:  Step 3 (Issue SW reset) ###########
$APP $DEV raw 0x0012 0x04  # master page select
$APP $DEV raw 0x0000 0x81  # reset

########### SCB:  Step 4 (Program analog trim registers on ADC page) 
#ADC32RFxx_LOWLEVEL
$APP $DEV raw 0x0012 0x00  # master page clear
$APP $DEV raw 0x0011 0xFF  # adc page select
$APP $DEV raw 0x0022 0xC0  # Table 102 match 
$APP $DEV raw 0x0032 0x80  # Table 102 match 
$APP $DEV raw 0x0033 0x08  # Table 102 match 
$APP $DEV raw 0x0042 0x03  # Table 102 match 
$APP $DEV raw 0x0043 0x03  # Table 102 match 
$APP $DEV raw 0x0045 0x58  # Table 102 match 
$APP $DEV raw 0x0046 0xC4  # Table 102 match 
$APP $DEV raw 0x0047 0x01  # Table 102 match 
$APP $DEV raw 0x0053 0x01  # Table 102 match 
$APP $DEV raw 0x0054 0x08  # Table 102 match 
$APP $DEV raw 0x0064 0x05  # Table 102 match 
$APP $DEV raw 0x0072 0x84  # Table 102 match 
$APP $DEV raw 0x008C 0x80  # Table 102 match 
$APP $DEV raw 0x0097 0x80  # Table 102 match 
$APP $DEV raw 0x00F0 0x38  # Table 102 match 
$APP $DEV raw 0x00F1 0xBF  # Table 102 match 
$APP $DEV raw 0x003F 0x00  # Not in table 102. In forum script.
$APP $DEV raw 0x00F8 0x00  # Not in table 102. In forum script.

########### SCB:  Step 5 (Program analog registers on master page) 
$APP $DEV raw 0x0011 0x00  # adc page clear
$APP $DEV raw 0x0012 0x04  # master page select
#ADC32RFxx_LOWLEVEL
$APP $DEV raw 0x0000 0x00  # Not in table 102. In forum script. 
$APP $DEV raw 0x0020 0x00  # Powerdowns,  In forum script. 
$APP $DEV raw 0x0025 0x01  # Table 102 match
$APP $DEV raw 0x0026 0x40  # Table 102 match
$APP $DEV raw 0x0027 0x80  # Table 102 match
$APP $DEV raw 0x0029 0x40  # Table 102 match 
$APP $DEV raw 0x002A 0x80  # Table 102 match 
$APP $DEV raw 0x002C 0x40  # Table 102 match 
$APP $DEV raw 0x002D 0x80  # Table 102 match 
$APP $DEV raw 0x002F 0x40  # Table 102 match 
$APP $DEV raw 0x0034 0x01  # Table 102 match 
$APP $DEV raw 0x0039 0x50  # CHA/B pd n control, sync term dis.  In forum script. 
$APP $DEV raw 0x003B 0x28  # Table 102 match 
$APP $DEV raw 0x003C 0x00  # Sysref delay.  In forum script.
$APP $DEV raw 0x003D 0x00  # JESD Output Swing.  In forum script.
$APP $DEV raw 0x003F 0x01  # Table 102 match 
$APP $DEV raw 0x0040 0x80  # Table 102 match 
$APP $DEV raw 0x0042 0x40  # Table 102 match 
$APP $DEV raw 0x0043 0x80  # Table 102 match 
$APP $DEV raw 0x0045 0x40  # Table 102 match 
$APP $DEV raw 0x0046 0x80  # Table 102 match 
$APP $DEV raw 0x0048 0x40  # Table 10 2 match 
$APP $DEV raw 0x0049 0x80  # Table 102 match 
$APP $DEV raw 0x004B 0x40  # Table 102 match 
$APP $DEV raw 0x0053 0x60  # Table 102 match 
$APP $DEV raw 0x0058 0x00  # syncb pol
$APP $DEV raw 0x0059 0x02  # Table 102 match 
$APP $DEV raw 0x005A 0x00  # Sysref delay.  In forum script.
$APP $DEV raw 0x005B 0x08  # Table 102 match 
$APP $DEV raw 0x005C 0x07  # Table 102 match 
$APP $DEV raw 0x0062 0xE0  # Table 102 match 
$APP $DEV raw 0x0065 0x81  # Table 102 match 
$APP $DEV raw 0x0066 0x80  # undoc 
$APP $DEV raw 0x006B 0x04  # Table 102 match 
$APP $DEV raw 0x006C 0x08  # Table 102 match 
$APP $DEV raw 0x006E 0x80  # Table 102 match 
$APP $DEV raw 0x006F 0xC0  # Table 102 match 
$APP $DEV raw 0x0070 0xC0  # Table 102 match 
$APP $DEV raw 0x0071 0x03  # Table 102 match 
$APP $DEV raw 0x0076 0xA0  # Table 102 match 
$APP $DEV raw 0x0077 0x0A  # Table 102 match 
$APP $DEV raw 0x007D 0x41  # Table 102 match 
$APP $DEV raw 0x0081 0x18  # Table 102 match 
$APP $DEV raw 0x0084 0x55  # Table 102 match 
$APP $DEV raw 0x008A 0x41  # Table 102 match 
$APP $DEV raw 0x008E 0x18  # Table 102 match 

########### SCB:  Step 6 (Program final trim regs on ADC page) 
$APP $DEV raw 0x0012 0x00  # master page clear
$APP $DEV raw 0x0011 0xFF  # adc page select
$APP $DEV raw 0x0083 0x07  # Table 103 match 
$APP $DEV raw 0x005C 0x01  # Table 103 match
$APP $DEV raw 0x0011 0x00  # adc page clear
# $APP $DEV raw 0x4001 0x00  # Q: What does this do? Removing.
# $APP $DEV raw 0x4002 0x00  # Q: What does this do? Removing.

########### SCB:  Step 7 (Enable interleaving correction) 
#ADC32RFxx_MAIN_DIG
$APP $DEV raw 0x4004 0x68  # Main Digital Page Select (Nyquist chA)
$APP $DEV raw 0x4003 0x00
$APP $DEV raw 0x4002 0x00
$APP $DEV raw 0x6044 0x20  # LOOP EN1. Used to be 0x60
$APP $DEV raw 0x6068 0x40  # LOOP EN2
$APP $DEV raw 0x60A2 0x09  # nq zone
#ADC32RFxx_LOWLEVEL
$APP $DEV raw 0x608D 0x50  # undoc
$APP $DEV raw 0x608B 0x05  # undoc
#ADC32RFxx_MAIN_DIG
$APP $DEV raw 0x4004 0x68  # Main Digital Page Select (Nyquist chB)
$APP $DEV raw 0x4003 0x01
$APP $DEV raw 0x4002 0x00
$APP $DEV raw 0x6044 0x20  # LOOP EN1. Used to be 0x60
$APP $DEV raw 0x6068 0x40  # LOOP EN2
$APP $DEV raw 0x60A2 0x09  # nq zone
#ADC32RFxx_LOWLEVEL 
$APP $DEV raw 0x608D 0x50  # undoc
$APP $DEV raw 0x608B 0x05  # undoc

########### SCB:  Step 8 (Issue SW reset) 
$APP $DEV raw 0x4004 0x68  # Main Digital Page Select (Nyquist chA)
$APP $DEV raw 0x4003 0x00
$APP $DEV raw 0x4002 0x00
$APP $DEV raw 0x6000 0x00  # seems to be main digital page reset
$APP $DEV raw 0x7000 0x00  # unsure wh y channel bit is toggled
$APP $DEV raw 0x6000 0x01
$APP $DEV raw 0x7000 0x01
$APP $DEV raw 0x6000 0x00
$APP $DEV raw 0x7000 0x00

########### SCB:  Step 9 (Set registers for digital bank) 
#ADC32RFxx_DIGITAL
$APP $DEV raw 0x4004 0x69  # JESD Digital Page Select
$APP $DEV raw 0x4003 0x00  # chA = 0x6xxx, chB = 0x7xxx
$APP $DEV raw 0x4002 0x00
$APP $DEV raw 0x6001 0x80  # ctrl k
$APP $DEV raw 0x6002 0x0F  # 12 bit mode
$APP $DEV raw 0x6003 0x01  # These will be removed.  Put in ramp mode.
$APP $DEV raw 0x6004 0x00  # Rel ILA Seq
$APP $DEV raw 0x6006 0x00  # Scramble control
$APP $DEV raw 0x6007 0x0F  # frames per multifram
$APP $DEV raw 0x6016 0x00  # 40x Mode 
$APP $DEV raw 0x6032 0x0C  # de-emphasis
$APP $DEV raw 0x6033 0x0C  # de-emphasis
$APP $DEV raw 0x6034 0x0C  # de-emphasis 
$APP $DEV raw 0x6035 0x0C  # de-emphasis 
$APP $DEV raw 0x6036 0x00  # cmos syncb control
$APP $DEV raw 0x6037 0x01  # pll mode
$APP $DEV raw 0x603E 0x00  # From ramp script.
$APP $DEV raw 0x7001 0x80  # ctrl k
$APP $DEV raw 0x7002 0x0F  # 12 bit mode
$APP $DEV raw 0x7003 0x01  # These will be removed.  Put in ramp mode.
$APP $DEV raw 0x7004 0x00  # Rel ILA Seq
$APP $DEV raw 0x7006 0x00  # Scramble control
$APP $DEV raw 0x7007 0x0F  # frames per multifram
$APP $DEV raw 0x7016 0x00  # 40x Mode 
$APP $DEV raw 0x7032 0x0C  # de-emphasis
$APP $DEV raw 0x7033 0x0C  # de-emphasis
$APP $DEV raw 0x7034 0x0C  # de-emphasis 
$APP $DEV raw 0x7035 0x0C  # de-emphasis 
$APP $DEV raw 0x7036 0x00  # cmos syncb control
$APP $DEV raw 0x7037 0x01  # pll mode
$APP $DEV raw 0x703E 0x00  # From ramp script.

########### SCB:  Step 10 (Pulse SYNCB from low to high to xmit K28.5 sync mode) 
# turn off continunous sysref
cird /dev/spi.macb-dsbfpga << EOF
# adc_enable
adc sysref disable
quit
EOF

over 5 years ago

0 Yusuf%20Agoro over 5 years ago

TI__Expert 4880 points

Shawn,

We have forwarded your question to a device expert and they should get back with you shortly.

Yusuf

0 Shawn Bish over 5 years ago in reply to Yusuf%20Agoro

Prodigy 170 points

Thank you.

0 jim s over 5 years ago in reply to Shawn Bish

TI__Guru* 91947 points

12bit_ramp_82820_mode_register_settings.cfgShawn,

Using our hardware, which uses an Altera Arria V device, I cannot duplicate this issue when using your settings. By default, our ADC GUI sets the de-emphasis to -6.2dB. I configured the ADC for ramp mode and attached the configuration file used by the ADC during this test.

Have you tried using a different frequency that did not require so many decimal points such as 2600MHz or 2500MHz? Did you try slowing down the serdes lane rate to see if it helps?

Regards,

Jim

0 Shawn Bish over 5 years ago in reply to jim s

Prodigy 170 points

Jim,

I was able to solve my issue today. The target output frequency of my FPGA JESD clock synthesizer wasn't set to the correct frequency with enough bits of precision. I am now up and running with no bit errors in the ADC ramp signal.

Thanks, Shawn

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ADC32RF45: Bit errors in samples received by Xilinx JESD core