Part Number: ADS8920B
Hi TI community,
I'm working on a design that uses the DAC8830 to generate sinusoids in the kilohertz range. The design currently uses an MCP3550 chip from Microchip (datasheet linked here) as a differential ADC, but its conversion time is far too slow to handle these frequencies.
I found the ADS892xB chip, and it seems suitable for this frequency range with good resolution. The MCP3550 had a 3-wire SPI interface, but I see that the ADS8920b has several serial digital outs as well as a serial digital in. Can this device still be operated with 3-wires? There is also a "CONVST" pin which I'm not sure what to do with for this application.
Also could the ADS8920b share a serial clock with the DAC8830? As long as we can control the DAC's sample rate, the ADC just has to be fast enough to sample the generated signal.
Thanks a lot for your time,
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In reply to Keith Nicholas:
Thank you for the timely response.
Looking at figure 88, it looks like /RST is tied to DVDD (5 V) through a resistor. What resistance would you recommend if one is needed? Also for a 3 pin configuration I should leave /RVS floating correct?
Above figure 56, the datasheet mentions writing to the SDO_CNTL and SDI_CNTL registers to select my SPI protocol. How would I do this in a 3 pin configuration with a grounded SDI pin? Is there some way to configure/calibrate the device with 3 pins, and will the lack of an SDI therefore affect the accuracy of the results?
For figure 46, since my CONVST would be tied to my /CS, is the conversion initiated by a falling edge instead? I'm confused about when this quiet period would occur as a result.
Thanks a lot for the help,
In reply to Ian Murray11:
Thanks a lot for the information. The design uses a reference voltage of 2.5 V so it sounds like we'll need an SDI line after all.
Now that you mention some timing constraints, I was testing the reference design in TINA, and in the schematics it specified:
"THIS MODEL WILL NOT PROVIDE ACCURATE SIMULATION OF DIGITAL TIMING PERFORMANCE"
Do you know in what respects the model is limited? Do you have any recommendation for verifying the digital timing performance of the design?
Hi Keith, Thanks for the timely response. There is a table at the start of the datasheet that lists SPI clock requirements for 1 MSPS. Is there a way to determine the required clocks for other sampling rates? Also, what are the requirements for using the 'enhanced' SPI protocol? (And is this different from 'multiSPI'?) Since it looks like the digital control lines are going to operate in the MHz range, is there any additional circuitry recommended to maintain signal integrity? If it helps inform your answer, the chip will be controlled with a Spartan-6 FPGA, and the digital signals will be buffered using a TXB0108 bi-directional level shifter.
Finally, if my design requires two ADS8920bs operating with the same configuration but sampling different values, do you see any problems using common SCLK, /CS, and SDI lines for them? (But still keeping separate SDO lines for the different readings). Thanks a lot! Ian
Take a look at section 7.5.3 in the datasheet which describes two data transfer time zones (Zone 1 and Zone 2). Zone 1 is the standard SPI transfer zone; Zone 2 is referred to as part of Enhanced SPI. MultiSPI refers to multiple SDO lines, but can also be thought as part of 'enhanced SPI' as well. Basically, Zone 2 allows a larger percentage of the cycle time to be used to read data out of the device, which lowers the SPI SCLK speed requirements. Reading in Zone 2 is controlled by the host timing (SCLK relative to the /CS, CONVST edge). MultiSPI requires writing to the configuration registers to enable multiple SDO lines (1x, 2x, 4x).
There is a good White Paper that describes all of this in more detail.
The table on the front page of the datasheet is approximate and assumes a single SDO line reading in Zone 2. Use the values in section 6.6, Timing Requirements, and equations 8 and 9 in section 7.5.3, to calculate the exact minimum SCLK frequency for different sampling rates.
Tread-z2=1250nS-20nS-30nS=1200nS (equation 8)
Fsclk=16/1200nS=13.33MHz for 16b data transfer (equation 9)
Fsclk=18/1200nS=15MHz for 18b data transfer (16b data plus 2 parity bits)
It never hurts to include a 10ohm series resistor in each digital line. This helps with high speed digital edges that could couple additional noise into the ADC. Depending on the FPGA used, you can usually slow the edge rates down. The ADS8920BEVM evaluation board has resistors, but just uses 0 ohm jumpers. I suggest using the EVM design and layout as a good starting point.
Sharing the digital lines (except SDO) between multiple ADS8920B devices will not be an issue. The only limitation is that each device will be configured identically.
Thanks so much for all the consultation.
I'm just trying to interpret the enhanced SPI requirements- it seems most of them utilize other digital lines. If we go with the 4 wire (/CS, SCLK, SDI, SDO) architecture, is 52 MHz the minimum clock rate needed for 1 MSPS performance? Ideally we would be able to get it a bit lower than this without running another digital line.
Using Zone 2 for reading 16b conversion data will require 18MHz SCLK speed using only 4 wires. If you want to read the parity bits, the clock speed will be slightly higher, ~20MHz.
Hope this helps clear things up.
I see what you're saying... but when you say 4 wires, is the 4th wire connected to SDI? From the datasheet I thought enhanced SPI required the use of a different pin such as CONVST.
Thanks again for your time,
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