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Part Number: DAC38RF82
THE FPGA can't configure the output pin level to the CML, then how to understand the cml level?? The FPGA GTH pin how to connect with the DAC RX[0:7] interface?
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The FPGA must be able to support the physical layer of the JESD204B standard if it is to work with the JESD204B DAC38RF82. What FPGA are you trying to use? If the transceivers support the standard, it will work with this part.
In reply to jim s:
We will use xilinx Kintex UltraScale FPGA KU060,which is able to support the JESD204B standard.The design is below,The DAC_RXP7and DAC_RXN7 are the FPGA GTH differential pins,which are connect with the DAC38RF82 pins RX7P and RX7N .Could you help me evaluate the design is available?
In reply to William Wong:
Under the DAC38RF82EVM product folder on the TI website you can download an example firmware project that is used with a Xilinx KCU105 evaluation board to interface to a DAC38RF82EVM. You find other examples as well on the Xilinx website.
If we could select the DAC B output when DAC38RF82 is working in only one DAC mode ?
DAC B is not available in single DAC mode.
Yes, you can turn off a channel by disabling the TXEN signal. There is a software register for both channels so you can turn off either one or both.
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