DAC38RF82: DAC38RF82 RX[0..7] input channnel electrical level(CML)

Wong

Part Number: DAC38RF82

THE FPGA can't configure the output pin level to the CML, then how to understand the cml level?? The FPGA GTH pin how to connect with the DAC RX[0:7] interface?

over 5 years ago

0 Jim Brinkhurst1 over 5 years ago

TI__Mastermind 43860 points

Hi William
We have received your question. One of our DAC experts will provide a more detailed response soon.
Best regards,
Jim B

0 jim s over 5 years ago

TI__Guru* 91947 points

William,

The FPGA must be able to support the physical layer of the JESD204B standard if it is to work with the JESD204B DAC38RF82. What FPGA are you trying to use? If the transceivers support the standard, it will work with this part.

Regards,

Jim

0 Wong over 5 years ago in reply to jim s

Intellectual 570 points

We will use xilinx Kintex UltraScale FPGA KU060,which is able to support the JESD204B standard.The design is below,The DAC_RXP7and DAC_RXN7 are the FPGA GTH differential pins,which are connect with the DAC38RF82 pins RX7P and RX7N .Could you help me evaluate the design is available?

0 jim s over 5 years ago in reply to Wong

TI__Guru* 91947 points

William,

Under the DAC38RF82EVM product folder on the TI website you can download an example firmware project that is used with a Xilinx KCU105 evaluation board to interface to a DAC38RF82EVM. You find other examples as well on the Xilinx website.

Regards,

Jim