TSW14J56EVM: trigger capability and TSW14xx synchronization
Part Number: TSW14J56EVM
I need to modify the TSW14J56 firmware to allow multiple captures before offloading data. I downloaded the firmware provided, but with no modifications it doesn't compile successfully in Quartus II 14.1, which I believe is the environment it was developed in. Compilation yields the following error:
Error (125091): Tcl error: ERROR: Option "-qip" for "UNFORCE_MERGE_PLL_OUTPUT_COUNTER" assignment is illegal. Specify a legal option or remove the option.
while executing"set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*jesd_avgz_pll_0002*|altera_pll:altera_pll_i*|*"" (file "gzPLL/jesd_avgz_pll/jesd_avgz_pll_0002.qip" line 2) Info (125063): set_global_assignment -name QIP_FILE gzPLL/jesd_avgz_pll/jesd_avgz_pll_0002.qip -qip gzPLL/jesd_avgz_pll.qip -library jesd_avgz_pll
The file mentioned contains only two lines:
set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*jesd_avgz_pll_0002*|altera_pll:altera_pll_i*|*"set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*jesd_avgz_pll_0002*|altera_pll:altera_pll_i*|*"
Why doesn't the provided firmware compile? Am I making some mistake? I have only worked with VHDL and Xilinx boards before, so I am new to both Verilog and Quartus.
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The TSW14J56 firmware was developed with Quartus II 14.0, not 14.1. This issue may be due to version difference. Can you try compiling with Quartus version14.0?
There could be an upgrade in the PLL IP or settings change between 14.0 and 14.1 versions which is causing the issue.
Can you try deleting the PLL IP listed with errors, add it again to the design and start compilation?
In reply to jim s:
I am working on getting 14.0 working, but am having some issues getting it to contact our license server. I would rather just use the original development software than spend a bunch of time trying to reconcile IP updates. For now, I am using the evaluation license and the firmware still won't compile. Here is a screenshot of the analysis & synthesis errors.
In reply to Darren Midkiff56:
I am checking with the firmware team regarding this. Have you tried contacting Intel (Altera) regarding this issue?
More info has been provided by our firmware team in the attached document.
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