ADS52J90: Traces length matching of the JESD pairs

Hi Vladica,

Thanks for using ADS52J90 device.

For your questions of using JESD, I would like to ask our team manager

and will reply to your in about 2 days.

Thank you!

Best regards,

Chen

Hi Chan,

Thanks for the info. I would be waiting for the answer.

Best regards,
Vladica

Hi Vladica,

On our ADS52J90EVM board which is using LMK04826, we include the JESD output signal connector
underneath of the board which is connected to TSW14J56EVM to capture output data.
for your question, could you please first take a look at the User's Guide as:
www.ti.com/.../slau632b.pdf
(inside this file, from page34 to page44, it shows you the schematics.)
Also I am continuing to talk to the group manager for more question.

Thank you!

Best regards,
Chen

Hi Chen,

I know the Users Guide and there it is specified that they should be matched length. Anyway, in the Datasheet of the ADC, for the JESD lanes it is written that the matched length is not so important as for LVDS. The question is what this means? Hom much can be the difference between the different JESD pairs?

Best regards,

Vladica

Hi Vladica,

Thank you for your question for ADS52J90 device.
Yes, All the output data from LVDS mode (such as DOUTs, FCLK, and DCLK)
are sent out together and synchronously from ADS52J90
(as long as all the trace lengths are matched.)
which is totally different from JESD mode.
such as:
1) All CML OUT signals are from ADS52J90 and will be sent to FPGA
(so for these trace lengths needed to be matched.)
2) CLK, SYSREF (both used for ADS52J90) are coming from LMK to ADS52J90
(so these two trace pairs length must be matched.)
3) also another CLK, SYSREF, GTXCLK (they are used for FPGA)
are coming from LMK to FPGA
(so these three trace pairs length must be matched.)
However, #1, #2, and #3 these three options seem like they don't need to
be matched with each other when using JESD mode.

Yes, I will continue to confirm this question with our group engineer.

Thank you!

Best regards,
Chen