• State
  • Locked Locked
  • Replies 8 replies
  • Subscribers 47 subscribers
  • Views 718 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TSW14J56EVM: Intel-Altera license for JESD204

GEORGE CONRAD
Prodigy 50 points

Part Number: TSW14J56EVM

I'm new to the TSW14J56EVM and this forum, but haven't found an answer in searching earlier posts....

When I compile the downloaded .qar, I get:

"Info (115017): Design contains a time-limited core -- only a single, time-limited programming file can be generated"

We want to add some functionality to the Arria FPGA (without touching the JESD IP) but it appears we can't without purchasing a license from Intel-Altera for their JESD IP ($20k).

Since we're using the TSW14J56EVM (6) for a "proof-of-concept" project, $20k is more than we can justify.

Am I understanding this situation correctly?

If so, what do you suggest?

Thanks,

George C.

  • 0
    TI__Genius 10505 points
    Hi George,

    I have forwarded your question to our TSW14J56EVM expert and he will get back to you.

    Regards,
    Vijay
  • 0
    TI__Guru* 91947 points

    George,

    The only thing I can think of is to use the 30 day free trial license, create a .sof file, and load this file to the FPGA through the JTAG connector.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 50 points

    Thanks for your response Jim.  I've considered  your suggestion (i.e. "30 day free trial license") and also looked into Altera's IP license "tethering".

    In both cases, I run into trouble. We have six of the TWW14J56EVM each with 8 ADC/DAC channels attached. I expect many iterations before we figure out all the control/sync functionality that I'll need to add to the Arria V GZ. I expect it to take more than 30 days and tethering isn't practical for this many EVMs.

    I realize the EVM was never intended for a "demo" situation like this, but I hoped that TI might have a contact at Intel-Altera and some leverage to get us an extended temp license for the JESD IP until we can do our proof-of-concept demo. If that demo is successful, we'll have the money to design out the six EVMs with our own custom board (that includes Altera's FPGA with a purchased JESD IP license, not to mention lots of TI ADC/DACs). 

    I'm also pursing this directly with Intel-Altera, but am not getting much response (i.e. not finding the right "decision maker" in their hierarchy).

    Cheers,

    George

  • 0 in reply to GEORGE CONRAD
    TI__Guru* 91947 points

    George,

    Send me your email address and company info and I will pass it on to my Intel contacts.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 50 points
    Thanks Jim.

    ====== My contact info ======
    George Conrad, PE
    Radix2 Engineering, LLC
    19004 E. 10th Lane
    Greenacres, WA 99016
    509-844-4513 (mobile/text)
    www.linkedin.com/.../

    ====== The company I'm contracting with (and has the EVMs) ======
    Agile RF Systems LLC
    Berthoud, Colorado

    ====== CEO of Agile RF Systems ======
    P. Keith Kelly, PhD
    pkelly@agilerfsystems.com
    www.linkedin.com/.../
  • 0 in reply to GEORGE CONRAD
    Prodigy 50 points
    Thanks Jim, Rick S called me yesterday (4/16). He forwarded a request to get me a temp license for the JESD IP.
    Very prompt by both you & Rick !

    One additional question for you:
    I found a link you posted (6560.TSW14J56 RevD MC firmware design document.doc) in "TSW14J56EVM: Simulation doesn't work" (Dec 19, 2018 3:05 PM).
    It appears to document the AVGZ design that's on the TSW14J57EVM.
    It was useful, but it is labeled "RevD" (Rev1.0 Initial draft 2nd Dec 2014).
    Is there a newer version (corrected with more details) ?

    Regards,
    George C.
  • 0 in reply to GEORGE CONRAD
    TI__Guru* 91947 points

    George,

    The TSW14J57EVM uses an Arria 10 device. Both the TSW14J56 and 57 have example designs under the product folders on the TI website and the versions should be the latest.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 50 points

    Sorry for my typo Jim, but glad to know the difference between the 57 and 56.
    In regards to the example designs that you mentioned, I have looked at them and everything else I could find under the product folders. However, nothing comes close to the info in the MS Word doc ("6560.TSW14J56 RevD MC firmware design document.doc"). It has block diagrams, bus organization, and some theory of operation for the Arria V design. If only it were the final version and not a draft. This level of detail is very helpful to me since I'm trying to add some control/sync functionality to the existing design without "breaking" it.
    I have found one of the Soliton co-authors on LinkedIn. I'll try contacting him directly.
    Cheers.
    George C.