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ADS5295: Noisy data using external sampling clock at 50MHz

Part Number: ADS5295

ADS5295 evm and TSW1400 evm - problems using an external 50MHz sampling clock

Dear TI ADC team,

I am using the ADS5295 evm and TSW1400 evm and the associated ADS5295_96 GUI and HSDC Pro control software.

When using the on board oscillator operating at 80MHz, I get "clean" 12bit data on all eight channels - no dropouts in the time data, and a "clean" FFT at the carrier (testing at 3.111MHz and 30.111MHz).

When I use an external oscillator operating at 80MHz and 1.8Vp-p using the transformer input outlined in Diagram 3 on pages 31 and 32 of the ADS5295 Users Manual (SLAU442 Nov 2012), I also get 
clean" data captures.

However, when I use a 50MHz sampling clock (again at 1.8Vpp), I get "noisy" data, especially on channel 1; the FFT has an increased noise floor, and one can clearly see drop outs in the time data sequence.

I am wondering if I need to change LVDS settings in the ADS5295 GUI software when I change the external sampling clock frequency.

I need to figure this out so I can use the ADS5295 with an alternative FPGA and processor in another design, so I appreciate any guidance.

Thanks!

  • Hello John,

    Welcome to TI E2E forum!

    Thank you for the interest in the ADS5295 device.

    I will check your conditions on our EVM and will get back to you by Wednesday.
    Can you attach the FFT plots of the clean and noisy data?
  • John, 

    not quite sure i f you solve the problem Praveen is out. 

    i think you will need to enter the 50Mhz number into the HSDC Pro GUI. Then the LVDS IP knows the timing setting. from your descripiton, it looks like a LVDS timing capture issue. 

    by the way, the device can work at 80MSPS, there is no reason it doesn't work at a lower speed like 50MSPS. when you see that issue, you can first run a RAMP test patttern and see whether the LVDS capture is clean. 


    Thanks!