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ADS54J64EVM: evaluate mode 6

Part Number: ADS54J64EVM
Other Parts Discussed in Thread: ADS58J64, LMK04828, , ADS54J64, ADS58J64EVM

Hello

The mode 6 (IQ 125MSPS) is not supported in HSDC pro software. We would like to try it in our carrier board with FMC connector.

Is still possible set the mode 6 with ADS58J64 EVM GUI (JP3 set to USB mode)?

We would like to bypass CPLD with JP3 set to FMC mode.

What is funcionality of CPLD in this configuration?

What is purpose of signals FMC_D5, FMC_D6 and FMC_DIR_CONTROL?

Thanks and Regards

Daniel

  • Hey Daniel, 

    We are looking into your question and will get back to you ASAP. 

    Yusuf

  • Daniel,

    We are looking into creating an option to add this mode to HSDC Pro.

    The firmware for the CPLD is attached. In FMC mode, the CPLD disconnects the SPI signals from the FTDI device and connects them to the FMC connector. It is basically functioning as a mux. FMC_D5 and D6 are spare signals. FMC_DIR_CONTROL is to be used when using the ADC or LMK in 3 wire SPI mode to control the direction of the data. See the firmware for more information regarding this.

    Regards,

    Jim

    ADS54J64EVM CPLD Code.zip

  • Daniel,

    You can use the "ADS58J64_LMF_4841_mode01" option in HSDC Pro with the ADC operating in mode 6. Before you try to capture data, after loading the mode 6 option for the ADC, go to the LMK04828 tab on the ADC GUI and change the CLKout 0 and 1 DCLK Divider to 24. If sampling at 983.04Msps, enter 122.88M for the ADC Output Data Rate in the HSDC Pro GUI. 

    Regards,

    Jim

  • Hello

    Yesterday I have modified kit to use external clk (moved 100nF from C47/C48 to R35/R39). The kit was used in our proprietary board with Xilinx IP JESD core (LMFS=4841 K =32). The board generate low noise 1GHz clock into ADC through J6 connector and 125MHz reference clock to FPGA. LMK04828 is left in reset state so I assume that its outputs are power-down. I was able bring up the link and observed correct IQ samples (ADC data with sinus signals, test patterns etc).

    Today I had problem with establishing jesd communication what worked yesterday. The SYNC signal is not asserted because K28.5 (0xBC) is seen only on lanes B C and D. I don't know what happened...

    I´m using attached script for ADC configuration in mode 6. Can someone please check the sequence? The datasheet isn´t clear for me about setting the mode 6.

    Regards,

    Daniel

    skript.cfg

  • Daniel,

    Did you reset the ADC after the clocks were present and before loading the ADC config file? Can the ADC 5V supply provide 3A of current? Is the clock going to the FPGA the correct frequency?

    Regards,

    Jim

  • I always do hardware reset when clocks are present and stable. 5V supply is OK, it takes 700 - 900 mA when ADC is configured.

    Clock going to the FPGA is correct.

    I have switched ADS54J64EVM with another evm board from different vendor. It uses similar signals for JESD and needs 125MHz as reference clock for FPGA. It works so I assume the our carrier board is OK.

    I read in user guide for ADS54J64EVM that SYSREF signal is disabled after configuring the ADc. As I said the LMK chip is left without configuration so its outputs are disabled according to datasheet and what I see in GUI. Does the ADc need SYSREF pulses to start?

    Regards

    Daniel

  • Well

    We have fixed issue witth JESD. The cfg script has to contain text with ADS58J64 (for example GLOBAL_ADS58J64, SERDESXX_ADS58J64...) otherwise the ADc (ADS54J64) has incorrect configuration.

    Also we have found problems with GUI and ADc:

    In GUI the NCO freq (ADS58J64 Other) have problem with endianness.

    Ramp pattern (reg 91h) doesn't work in mode 6.

    GUI can activate "Debug Log, Log to File". Where the file can be found?

    Regards,

    Dan

  • Dan,

    If you double click on the lower left corner of the GUI near where it says "Idle", a log file will open. Once you click on a button in the GUI that does register writes, these write values will appear in the log window. If you click inside the log window, there are options that allow you to save the values shown.

    Regards,

    Jim

  • Thank you Jim.

    I have just discovered issue with NCO configuration in mode 6. When JESD starts and NCO frequency isn't set and left in default 0x0 state then JESD communication reports errors which leads to reseting link (SYNC signal is toggled).

    I have question about setting the NCOs across the channels. How to achieve NCO synchronization? I observe not-deterministic delays from POR to POR in signals when channels are fed from the same source and NCOs set to the same frequency.

    I have attached updated script.

    Regards,

    Daniel

    config.cfg

  • Dan,

    You need to do a reset after power up and then the NCOs will be reset using the SYSREF signal.

    Regards,

    Jim

  • Thanks

    I have fixed problems with JESD stability and NCO.

    Now I'm facing problem with full-scale behaviour of the ADc. ADS54J64 should have full-scale range 1.1V so with 50ohm input it should have circa 4.8 dBm.

    I observe full-scale swing on the IQ data when the kit ADS54J64EVM is fed with circa 7-8dBm. I have checked voltage on differental inputs that swing is circa 1.5V. Also FOVR (set to -0.5 dBFS) functionality indicates overrange when swing exceeds circa 1.45V. The power from signal generator was also checked that it is 8 dBm

    Why I observe full-scale circa 1.5 V and not 1.1V? Do I overlook something?

    Regards,

    Dan

  • Dan,

    Do you have the pass band of the decimation filter set correctly? In the CHX page, try setting address 0x78 to 0x03.

    Regards,

    Jim

  • Jim,

    I'm basically interested in VHF band 90–110 MHz. This is reason why I select LPF config and first Nyquist zone. NCO in mode 6 is set for circa 90 MHz.

    The ADS58J64EVM is evaluated in TSW14J56EVM and in our Xilinx board where I can see separated IQ outputs from JESD. I can still confirm that full scale is around 8 dBm and not for 4.8 dBm.

    I have attached screens from High speed data converter for circa 4 dBm. Also I can't interpret complex FFT. It seems there is unbalance in IQ data.

    Regards,

    Dan

  • Hi

    The problem with full-scale in mode 6 can be fixed with using mixer compensation (don't know why it is disabled by default) and with digital gain (sampler level) for expense of NSD degratation.

    The problem with IQ imbalance in mode 6 still remains. IQ lanes are swapped  and one of the channel is one sample delayed to the other (see attachment I vs Q). I have reproduced it in our evaluation board.

    Can you please help me? I still believe there is something wrong with register configuration sequence for mode 6. The log from ADS58J64 EVM GUI doesn't make sense according to datasheet. The are several writes into undocummented registers etc.

    I vs Q

  • Dan,

    I am just returning from vacation and behind on many posts. I will try to look into this issue ASAP but this may take a few days.

    Regards,

    Jim

  • Hello Jim,

    I tried to do some reverse engineering with ADc configuration but I was unable to get it work correctly. The problem with IQ imbalance in mode 6 remains unsolved. :(

    Regards,

    Dan

  • Hello

    just update for someone facing similar problem.

    We have temporary fixed the problem with IQ unbalance by doing correction in our FPGA. Basically we swapped lanes in correct order and shifted one sample in Q channel so I->Q is 90°. With this fix the performance (NSD, SNR, ENOB at 125MSPS) is usable for our application.

    The last problem we have with NCOs reset so the phase are aligned. We tried feed SYSREF input with bursts (before SYSREF powerdown, reg 0x6A:0x02) without a success. Is there something what should we be aware of?

    We have tried to feed ADc with 500MHz and use mode 1 for achieving 125MSPS output (cause of lower clock frequency and lower decimation the performance should be same) but we couldn't establish the JESD link (in TSW14J56EVM with user guide or in our FPGA board). SPI sequence is same except set the mode 1, reference clock for FPGA JESD RX 125MHz, JESD RX setting same...

    I have a question about the ADS58J64. Is it basically ADS54J64 with burst mode instead averaging funcionality? Is there chance it could work better with our desired configuration?

    Regards,

    Dan

  • Daniel,

    Mode 6 will work. Just set address 0xAD and 0xAE to 0x06.

    With JP3 set to FMC mode, the following signals from the FMC connector will be used by the CPLD to control the ADC and LMK SPI:

    FMC_SCLK, FMC_SDIO, FMC_SDO, FMC_SEN_ADC, and FMC_SEN_LMK.

    If you were to use the ADC or LMK in 3-wire SPI mode, the CPLD would use the FMC_DIR_CONTROL to determine if the data line is used for writes or reads. FMC_D5 and FMC_D6 are spare signals from the FMC.

    The CPLD source code is attached. If required, you can modify as needed by the controller driving the FMC pins.

    Regards,

    Jim  

    3652.ADS54J64EVM CPLD Code.zip

  • Today I had problem with establishing jesd communication what worked yesterday. The SYNC signal is not asserted because K28.5 (0xBC) is seen only on lanes B C and D. I don't know what happened...

    https://tutuapp.uno/ , https://9apps.ooo/ , https://showbox.kim/

  • Snow,

    Did you issue a hard reset to the ADC after the clock was present?

    Regards,

    Jim


  • I also have this problem, if someone has a solution, please tell me

  • John,

    Is the problem with the CPLD or using Mode 6?

    Regards,

    Jim