ADS54J64EVM: evaluate mode 6

Prodigy 130 points

Replies: 22

Views: 825

Part Number: ADS54J64EVM

Hello

The mode 6 (IQ 125MSPS) is not supported in HSDC pro software. We would like to try it in our carrier board with FMC connector.

Is still possible set the mode 6 with ADS58J64 EVM GUI (JP3 set to USB mode)?

We would like to bypass CPLD with JP3 set to FMC mode.

What is funcionality of CPLD in this configuration?

What is purpose of signals FMC_D5, FMC_D6 and FMC_DIR_CONTROL?

Thanks and Regards

Daniel

22 Replies

  • Hey Daniel, 

    We are looking into your question and will get back to you ASAP. 

    Yusuf

  • Guru 52415 points

    Daniel,

    We are looking into creating an option to add this mode to HSDC Pro.

    The firmware for the CPLD is attached. In FMC mode, the CPLD disconnects the SPI signals from the FTDI device and connects them to the FMC connector. It is basically functioning as a mux. FMC_D5 and D6 are spare signals. FMC_DIR_CONTROL is to be used when using the ADC or LMK in 3 wire SPI mode to control the direction of the data. See the firmware for more information regarding this.

    Regards,

    Jim

    ADS54J64EVM CPLD Code.zip

  • Guru 52415 points

    In reply to jim s:

    Daniel,

    You can use the "ADS58J64_LMF_4841_mode01" option in HSDC Pro with the ADC operating in mode 6. Before you try to capture data, after loading the mode 6 option for the ADC, go to the LMK04828 tab on the ADC GUI and change the CLKout 0 and 1 DCLK Divider to 24. If sampling at 983.04Msps, enter 122.88M for the ADC Output Data Rate in the HSDC Pro GUI. 

    Regards,

    Jim

  • In reply to jim s:

    Hello

    Yesterday I have modified kit to use external clk (moved 100nF from C47/C48 to R35/R39). The kit was used in our proprietary board with Xilinx IP JESD core (LMFS=4841 K =32). The board generate low noise 1GHz clock into ADC through J6 connector and 125MHz reference clock to FPGA. LMK04828 is left in reset state so I assume that its outputs are power-down. I was able bring up the link and observed correct IQ samples (ADC data with sinus signals, test patterns etc).

    Today I had problem with establishing jesd communication what worked yesterday. The SYNC signal is not asserted because K28.5 (0xBC) is seen only on lanes B C and D. I don't know what happened...

    I´m using attached script for ADC configuration in mode 6. Can someone please check the sequence? The datasheet isn´t clear for me about setting the mode 6.

    Regards,

    Daniel

    skript.cfg

  • Guru 52415 points

    In reply to Daniel Stindl:

    Daniel,

    Did you reset the ADC after the clocks were present and before loading the ADC config file? Can the ADC 5V supply provide 3A of current? Is the clock going to the FPGA the correct frequency?

    Regards,

    Jim

  • In reply to jim s:

    I always do hardware reset when clocks are present and stable. 5V supply is OK, it takes 700 - 900 mA when ADC is configured.

    Clock going to the FPGA is correct.

    I have switched ADS54J64EVM with another evm board from different vendor. It uses similar signals for JESD and needs 125MHz as reference clock for FPGA. It works so I assume the our carrier board is OK.

    I read in user guide for ADS54J64EVM that SYSREF signal is disabled after configuring the ADc. As I said the LMK chip is left without configuration so its outputs are disabled according to datasheet and what I see in GUI. Does the ADc need SYSREF pulses to start?

    Regards

    Daniel

  • In reply to Daniel Stindl:

    Well

    We have fixed issue witth JESD. The cfg script has to contain text with ADS58J64 (for example GLOBAL_ADS58J64, SERDESXX_ADS58J64...) otherwise the ADc (ADS54J64) has incorrect configuration.

    Also we have found problems with GUI and ADc:

    In GUI the NCO freq (ADS58J64 Other) have problem with endianness.

    Ramp pattern (reg 91h) doesn't work in mode 6.

    GUI can activate "Debug Log, Log to File". Where the file can be found?

    Regards,

    Dan

  • Guru 52415 points

    In reply to Daniel Stindl:

    Dan,

    If you double click on the lower left corner of the GUI near where it says "Idle", a log file will open. Once you click on a button in the GUI that does register writes, these write values will appear in the log window. If you click inside the log window, there are options that allow you to save the values shown.

    Regards,

    Jim

  • In reply to jim s:

    Thank you Jim.

    I have just discovered issue with NCO configuration in mode 6. When JESD starts and NCO frequency isn't set and left in default 0x0 state then JESD communication reports errors which leads to reseting link (SYNC signal is toggled).

    I have question about setting the NCOs across the channels. How to achieve NCO synchronization? I observe not-deterministic delays from POR to POR in signals when channels are fed from the same source and NCOs set to the same frequency.

    I have attached updated script.

    Regards,

    Daniel

    config.cfg

  • Guru 52415 points

    In reply to Daniel Stindl:

    Dan,

    You need to do a reset after power up and then the NCOs will be reset using the SYSREF signal.

    Regards,

    Jim