ADS42JB49EVM: JESD Link ILA sequence does not compatible with JESD204B protocal

Zhu,

The SYNC operation is inverted on this device. Once SYNC goes high, the part starts CGS. After CGS is completed, SYNC should be pulled low and the ADC will start the ILA sequence.

Regards,

Jim  

Hi Jim

   Thanks for the help.

   Actually, I have noticed the Sync pins of EVM board is wrong.

   I use KC705 with this EVM board, and I can control the Sync pin myself instead of use the Xilinx JESD204B IP.

   So I just pull the Sync to capture the whole process from CGS to ILA, and found the ILA is mismatch with the datasheet.

Zhu,

When you mentioned other chips match the protocol, what are these other chips? More ADS42JB49 parts or another family of devices? Can you send the configuration file you are loading into the ADC? Do you issue a hard reset after the clocks are present? Is SYNC stable? If not, this could explain this. From your first Chipscope screen shot, I can verify the link is stable.

Regards,

Jim

Hi Jim

     We use ADS54J60 before, the ILA sequence is correct.  

     We also use ADI chips, and they are also correct.

     The configuration is the pre-installed cfg, name ADS42JB49_EVM_LMF421_250M.cfg, installed with the software. 

     I'm sure the Sync is stable, we use FMC pin directly.

      From the Chipscope, you can see the link is stable. The problem is the ILA process sending extra K28.5 several times. 

      Is it possible for your to repeate this problem, it's quiet simple, use default cfg file, and just pull the SYNC~ signal using VIO, and observe the GTX channels signals, rxdata, rxcharisk and rxdisperr. I can also prepare the Vivado project for you.

Zhu,

This was an interop report created by Xilinx using the KC705 to test all JESD functionality with the ADS42JB69EVM. Based on this, and data from our test group, I believe the issue may with your FPGA. Which part are you using? How much current can your 5V input source?

Regards,

Jim