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ADS1262: IDAC rotation: symmetry in time

Part Number: ADS1262

I have an ads1262 configured with following reg values:

1263reg[0](id)=x03
1263reg[1](power)=x03
1263reg[2](interface)=x04
1263reg[3](mode0)=x32
1263reg[4](mode1)=x00
1263reg[5](mode2)=x0f
1263reg[6](inpmux)=x54
1263reg[xx](ofcal)=x00000000
1263reg[xx](fscal)=x00400000
1263reg[13](idacmux)=x76
1263reg[14](idacmag)=x0a
1263reg[15](refmux)=x11
1263reg[16](tdacp)=x19
1263reg[17](tdacn)=x19
1263reg[18](gpiocon)=x00
1263reg[19](gpiodir)=xc9
1263reg[20](gpiodat)=x00

As can be seen, it is using both Chop and IDAC rotation, set to 38400 SPS, delay of 17us, free running. I have purposely set the 2 Idac magnitudes as opposing extremes to see the rotation effect on the Idac pins.

In the attached scope shot, CH1 (yellow) is data ready pin and CH2 (blue) is IDAC1 output. This shot was taken with my microcontroller frozen, so as to clearly show the behaviour of the ADC in free-running.

With 17us delay before each conversion, I would expect each dataReady to take (207+17)= 224us which is what I see in the scope.

Now to the questions:

1) On page 44 of datasheet, it is mentioned that "the sequence repeats" for all succeeding conversions. Judging by the data ready signal I get, I am assuming that the sequence that repeats is the last 2 steps (conversion 3 and 4). In other words, since I am free running, the first output result is withheld only the very first time I sent the STARTADC, not in every cycle.Correct?

1b) Do equations 19 and 20 (page 63) matter when free-running? (I'm guessing not, as long as I don't change mux settings)

2) Since both chop and rotation are enabled and ADC free-running, is the data read at any given time already accounting for the average of the last 4 measurements? (Pages 44 and 84 describes this separately, each as the average of 2, but not the effect when rotation and chop together.)

Now zooming into the IDAC rotation vs the data ready signal:

3) I get a data ready only 2us after the Idac changes magnitude. I would have expected the data ready to be falling 224us after the IDAC started its rotation... Therefore I am guessing for this particular capture this data ready actually refers to the previous cycle, with IDAC1 at 3mA.

3a) if that is the case, why does IDAC start to rise so soon, from a very short period at 0 mA back to 3mA? In other words, why the "swapped(=0mA)" IDAC1 time length is so much shorter than the uninverted(3mA) one?

  • Hi Rafael!

    Great ADS1262 questions here!  I'll look into this for you and get you some resolution by Monday afternoon.

  • Hi Rafael,

    I can try to help answer your questions...

    1) Page 44 of the ADS1262 datasheet describes what happens with ONLY IDAC rotation enabled. With chopping enabled, there should be additional steps between the IDAC swapping to account for the input chopping.

    NOTE: The SINC5 filter will have to re-settle EACH TIME the input MUX swaps AINP and AINN; and also each time IDAC1 & IDAC2 are swapped. So the on-going or free-running conversion period will be limited by the digital filter settling time (the same way it would if you changed the MUX channel, for example).

    1b) Equation 20 only applies to the FIRST conversion’s latency. For on-going conversions I would expect the conversion period to follow td(STDR), as given by Table 17 (on page 63) in the ADS1262 datasheet.

    2) I haven't tried using both IDAC rotation and CHOP modes enabled at the same time so I'm not entirely sure, but I would expect that the output data will be the average of the last 4 conversion results. At the very least it would be the average of the last two conversions. I'll have to follow-up with you to confirm...

    3) If I understand correctly, the 2 us is the timing between the /DRDY rising edge and falling edge, is that correct?... If so, this is just the update time from the end of a conversion to when /DRDY goes low. The actual the conversion period is the time between /DRDY falling edges.

    3a) I think the IDAC Rotation function provides a break-before-make connection; therefore, the IDAC current droops during the “break” period (at the /DRDY rising edge since the conversion has competed), and then the IDAC current has to settle once again as the other IDAC is switched-in. Due to this settling time, you may want to program some additional delay (conversion start delay) to ensure that the next conversion is not affected by this settling error.

    FYI...Since you're performing a lot of averaging, you're probably concerned about achieving a very low noise conversion result. To help significantly improve the noise performance, I would consider using the 14.4 kSPS data rate, or perhaps the SINC1 filter at 7200 SPS. The data throughput won't be that much slower and you'll achieve much better noise performance, because these digital filters will do a better job of attenuating the high-frequency delta-sigma modular noise (as shown in Figure 20 of the datasheet). Since the noise above 8 kHz is not Gaussian, averaging will be less effective if you do not first attenuate this noise with the digital filter. The 38.4 kSPS data rate will place the digital filter's -3 dB cutoff frequency at 7.8 kHz, which will allow some of that modulator noise to pass through the filter.

  • Hi Rafael,

    I see that you did not accept my answer. Please let me know if you have additional questions that I can try to address. Thanks!

  • Hi Chris, thanks a lot for the insightful reply!

    Here some of my comments/further questions to your answers:

    1) And I am guessing this digital filter settling time would explain why SINC1 @ 7200 produces almost the same data rate as SINC5@14400, as SINC1 is zero latency, correct?

    2) A follow-up on this one would be nice, thanks!

    3) Right, I believe we are on the same page then: by the time I see the IDAC fall, the nearby data ready going high and then low refers to the previous conversion.

    3a) Your answer made me realise one basic thing I probably had understood wrongly: if I program one IDAC to 3ma and the other to 0, I will still not be able to see the rotation. This is because the rotation happens not in terms of rotating IDAC magnitude between the 2 pins but actually rotating the internal IDAC generator for a given pin. So one pin will always be 3ma and the other always 0ma: what rotates is whether the 3ma is generated by one of the internal IDAC source or the other. If that is the case, then indeed your suggestion that the "fall" in IDAC that I see is likely the break-before make action.

    3b) Right now I have a dealy of 17us, which seems fine considering that from the beginning of the break-before-make to the settling plateau of the IDAC it takes about 10us as seen on the scope shot. But is this delay started exactly at the same time the break happens? Also, does the sampling commence exactly at the end of the delay? I'm asking these 2 questions to know if it would be possible to have instead a smaller programmed delay in case the ADC itself has some intrinsic "lag" or delay of its own.

    In regards to the digital filtering and the settling time final comment, would you recommend any application note/ white paper about the trade-offs between the different filters and the sampling frequency? 
    I'm also worried that reducing the sampling frequency will mean having to reduce the cut-off freq of my Nyquist analog first order low pass filter as well, which would also mean longer settling times...

  • Hi Rafael,

    1) Yes, the SINC1 filter will be settled after 1 complete conversion period. However, note if you have step change mid-conversion, then the next conversion result will show a voltage that is about half-way between the step, and then the following conversion after that will reflect the settled voltage result.

    2) I discussed this with the digital designer and he confirmed that the ADS1262 will average the last four conversion results when CHOP and IDAC rotation are enabled.

    3) Correct, the next conversion will begin immediately after the current one completes.

    3a) Generally, IDAC rotation is used in  3-wire RTD applications where it is important for the IDAC currents to be very precisely matched in order to accurately compensate for voltage drops in the wiring.

    3b) There isn't any additional delay other than the programmable conversion start delay. The modulator will begin sampling the signal as soon as this delay time completes. To get a sense if your delay time is sufficient, you can experiment with different delays, average multiple conversion results, and then compare the averages with different delay times to determine how much delay time is required. However, I would consider increasing the delay time slightly more than necessary to account for possible RC tolerances.

    We have a good blog post about the different filter types here: https://e2e.ti.com/blogs_/archives/b/precisionhub/archive/2016/06/10/delta-sigma-adc-digital-filter-types-sinc-filters

    Keep in mind that you're controlling the "output data rate", not the "input sampling frequency". The ADS1262 is an oversampling ADC, and by adjusting the data rate you are only changing the oversampling ratio. Your analog anti-aliasing filter needs only to worry about attenuating signals that fall into the repeated passbands of the digital filter around the sampling frequency (which for the ADS1262 is fclk/8). You can find some additional datails about this here: https://e2e.ti.com/support/data-converters/f/73/p/826024/3069413#3069413