I have an ads1262 configured with following reg values:
1263reg[0](id)=x03
1263reg[1](power)=x03
1263reg[2](interface)=x04
1263reg[3](mode0)=x32
1263reg[4](mode1)=x00
1263reg[5](mode2)=x0f
1263reg[6](inpmux)=x54
1263reg[xx](ofcal)=x00000000
1263reg[xx](fscal)=x00400000
1263reg[13](idacmux)=x76
1263reg[14](idacmag)=x0a
1263reg[15](refmux)=x11
1263reg[16](tdacp)=x19
1263reg[17](tdacn)=x19
1263reg[18](gpiocon)=x00
1263reg[19](gpiodir)=xc9
1263reg[20](gpiodat)=x00
As can be seen, it is using both Chop and IDAC rotation, set to 38400 SPS, delay of 17us, free running. I have purposely set the 2 Idac magnitudes as opposing extremes to see the rotation effect on the Idac pins.
In the attached scope shot, CH1 (yellow) is data ready pin and CH2 (blue) is IDAC1 output. This shot was taken with my microcontroller frozen, so as to clearly show the behaviour of the ADC in free-running.
With 17us delay before each conversion, I would expect each dataReady to take (207+17)= 224us which is what I see in the scope.
Now to the questions:
1) On page 44 of datasheet, it is mentioned that "the sequence repeats" for all succeeding conversions. Judging by the data ready signal I get, I am assuming that the sequence that repeats is the last 2 steps (conversion 3 and 4). In other words, since I am free running, the first output result is withheld only the very first time I sent the STARTADC, not in every cycle.Correct?
1b) Do equations 19 and 20 (page 63) matter when free-running? (I'm guessing not, as long as I don't change mux settings)
2) Since both chop and rotation are enabled and ADC free-running, is the data read at any given time already accounting for the average of the last 4 measurements? (Pages 44 and 84 describes this separately, each as the average of 2, but not the effect when rotation and chop together.)
Now zooming into the IDAC rotation vs the data ready signal:
3) I get a data ready only 2us after the Idac changes magnitude. I would have expected the data ready to be falling 224us after the IDAC started its rotation... Therefore I am guessing for this particular capture this data ready actually refers to the previous cycle, with IDAC1 at 3mA.
3a) if that is the case, why does IDAC start to rise so soon, from a very short period at 0 mA back to 3mA? In other words, why the "swapped(=0mA)" IDAC1 time length is so much shorter than the uninverted(3mA) one?