DAC38RF82: DAC38RF82 JESD Link Configuration Error and Lane2 FIFO error

hello,Jim

               I added two registers(0x40B and  0x40C) values

 address                            data

 0x40B                             0x0064     

 0x40C                             0x2702

7200_LMFS_8212_Int_6X.cfgUser,

The config file I used for your setup is attached. I am not seeing the errors you are reporting. What value are you using for K and what is your RBD setting?

Regards,

Jim

Hello,Jim

         Thanks for your help,

       The value K and RBD in my design: K=20,RBD=19

Best Regards

User,

See if this document helps.

Regards,

Jim

 Board trouble-shooting tips.docx

Hello, Jim

         Thanks for your patient help,I will try it later

Best Regards

hello,Jim

1. We read register  0x64 to 0x6D ,the result sitll has errors ,It shown as below(DACLANE0_Error ~ DACLANE7_Error)

 DACLANE0_Error ~ DACLANE7_Error=0x2000

 DACLANE2_Error =0x2008

DACLANE0_Error ~ DACLANE7_Error=0x2000

 DACLANE2_Error =0x2008

2.The JESD204B Link chain between DAC and FPGA is  always attemping to establish

My design is attached:

DAC_38rf82.cfg

User,

Were you able to pass the NCO SYSREF test? What are you using for a clock source and SYSREF source? Are they from the same source?

Regards,

Jim

hello,Jim 

         Thanks for your help

1.our test detais:

(1) After power is applied and external reset is pulsed from low to high, bits [15:10] of 0x7F are 100000;

(2) We enable LANE0 to LANE7,register 0x14A=0xFF03 ;

we set NCO frequency 50MHz, register value : 0x11E=0xC71C,0x11F=0x1C71,0x120=0x01C7;

Setting address 0x27 in page 1 to use SYSREF as the SYNC source;0x127=0x2828;

If SYSREF is present:

               LANE0 to LANE7 has no signal;the DAC output will be a stable 50MHz

If SYSREF is disable:

               LANE0 to LANE7 has no signal;the DAC output will be many tones:

Pardon, I don't quite understand what is"NCO ONLY MODE".

2.our clock tree is as below:

(1) The chip HMC7044 generate reference clk and sysref to chip LMX2592 ,DAC38RF82, FPGA.

(2)All output clocks of  Chip HMC7044 have the same phase .

(3) HMC7044 Provide LMX2592_RefClk_120M to LMX2592 to generate synchronized clk Dev_Clk 7200M to DAC as DACCLK.

(4) In my opinon , LMX2592_RefClk_120M and sysref_10M is synchronized, Dev_Clk 7200M is deterministic with the sysref_10M.

User,

In NCO only mode, the JESD204B data is not used. This is good test mode to verify SYSREF is getting sampled properly by the DAC. For this test to be valid though, SYSREF cannot be a divide by 2 factor of the sample rate. For your test, please change SYSREF to something like 10.169MHz. With my LMK device, I used a divide by 177 instead of 180 for the test to create a fractional frequency. With this setting, if the SYSREF is getting sampled properly, the NCO output of the DAC will look like many frequencies. The reason for this is the NCO is being reset by the SYSREF, and this will cause the NCO frequency to keep changing to a different  frequency on every rising edge of SYSREF as SYSREF is not a integer divide down of the sample rate. If SYSREF is not received properly by the DAC, the NCO will not reset and the output will be a single frequency.

Regards,

Jim

hello,Jim

     Thanks for your help;Now I will describe our test details            

       (1)we change sysref from 10MHz to 10.169MHz,but it still exist errors,0x164~0x16c is 0x2000;

      (2)The SYNC signal is constantly from low to high;

      (3)We set NCO frequency 50MHz;We test NCO reset with sysref,when the sysref is present ;NCO output a single 50Mhz;

           In my opnion, DAC is not sample sysref ;We detect sysref is 10MHz , 900mV with oscilloscope;

 I don't know how to resolve this problem; please help me.

Best Regards

User,

SYSREF must be synchronized with DACCLK. I am not sure this is the case with your clocking tree. You must also meet setup and hold times for SYSREF, meet the common mode voltage of 0.5V if DC coupled, and have a swing of 800mV p-p. The SYNC will not be stable until the DAC registers SYSREF properly.

Regards,

Jim

hello,jim

      I'm sorry to trouble you again,

      (1)We have test DAC38RF82 again.We set resgister 0x424=0x1800, Don't Bypass sysref alignment logic,Enable sysref alignment status outputs.

     Reading resgister 0x05,the value is 0x0049;It means the sysrefphase3 state has been observed.

(2)we set NCO FTW= 0x006D3A06D3A0,fNCO=12MHz, SYSREF=10MHz;We also set 0x127=0x2828; 0x124= 0x0010;use all sysref to reset NCO;

when enable sysref ;NCO can be reset by sysref; As below 

(2)BUT,when disable sysref ,there is no signal output;I don't what is wrong ?

User,

I have duplicated everything mentioned above, and when I turn off SYSREF going to the DAC, I get a 12MHz clean output. How are you disabling SYSREF?you

Make sure you are not disabling the DACCLK as well.

From what I can tell about your results above, you are sampling SYSREF properly as long as every time you read register 0x05 (write a 0x0 first to clear it) you are getting the same sysrefphase state.

Regards,

Jim

Hi,Jim

  Thanks for your help ,Now I have solved the problem of NCO  is reset by sysref;

In my opinion,NCO need reset signal to transit from  Initialization state to normal operation state;Now ,I describe the details

(1) when enable sysref ;NCO can be reset by sysref; As below 

(2) consequentially ,we use FPGA VIO module disable sysref ,NCO can't be reset by sysref,dac output 12MHz signal 

Although,the sysref problem is solved,but,I have another question to need your help;

QUESTION:

We read register  0x64 to 0x6B ,the result sitll has errors ,0x64 to 0x6B=0x2000;It means link configuration error;

register configueration attachment upload below

Best Regards

4532.DAC_38rf82.cfg

Hi,Jim

      We change the Value of 0x14F from 0x1CC1 to 0x1C60;Then,we read register  0x64 to 0x6B ,the results  has no errors.

The JESD204B Link chain between DAC and FPGA is  established;

But, I don't known the reasons.

User,

You set bit 5 = "1" which will cause the DAC not to report any errors that occur during the ILA sequence.

Regards,

Jim

Hello,Jim

         Thanks for your help; For ILA sequence errors,could you give me some advices to analysis the issues?

Best Regards

Hello,Jim

          Today,I verifIed the ILA parameter  S,M ,HD of My Xilinx JESD204B IP is equal the  parameter of DAC38RF82; We set register 0x14E=0x0F4F;N’=16;N=16;HD=1;SCR=OFF;

     0x14C=0x1307;K=20,L=8;

    0x14D=0x0101;M=2,S=2;

    0x14B=0x1400;F=1,RBD=20;

    0x153=0x0100;

    0x154=0x9E61;

But,DAC  SYNC request for link configuration error.

User,

Are you saying that you can get an output if you disable the ILA sequence checker but not if this is enabled? If this is the case, I have seen this issue with other customers as well. The problem is that the FPGA IP and DAC IP is not following the same methodology when determining how to set the ILA parameters. In some cases, an IP will set the parameter to a value that is the value -1, and in other cases the value used is as is. If this is the case, the ILA sequencer will always report an error. In most cases, customers ignore the ILA checker as long as valid data is achieved.

Regards,

Jim 

Hello,Jim

            Thanks for your timely response,When I set bit 5 = "1" of  0x14F, The JESD204B Link chain between DAC and FPGA is always established,we can get an valid output data;

           If I set set bit 5 = "0" of  0x14F, DAC  SYNC  always request for link configuration error and no output data。

Jim,could we bypass this problem?

Best Regards

hello,Jim

     I want to add something

    If I set JESD_SYNC_REQ register 0x151=0x00DF,Bypass link configuration error;The JESD204B Link chain between DAC and FPGA is also established,we also can get an valid output data;

Best Regards

Hello,Jim

        Either "bit5=1" of 0x14F or ''bit 5=0" of 0x151,The JESD204B Link chain between DAC and FPGA is  always  established;DAC has data output;

 Jim,I'm going to block this out temporarily;Thank you for your help during these days;

Best Regards,

   William