• Resolved

DAC38RF82: DAC38RF82 JESD Link Configuration Error and Lane2 FIFO error

Intellectual 370 points

Replies: 23

Views: 441

Part Number: DAC38RF82

hello,Jim

             we are testing DAC38RF82 now, we face some problems and need your help;

Firstly,Project Requirements:

1.FDac(DACCLK)=7200M,External Diff Clk;

2.Single DAC(DAC A)

3. 1 IQ pairs

4. 8 serdes lanes

5.Interprolation=6

6.output IF analog signal=1.7GHz

7.LMFSHD=82121

8.sysref=10MHz

9.FPGA  GTH refclk=150MHz

 

Secondly,Our DAC38RF82 register configuration :

 address                            data

  0x00                              0x7860

  0x01                              0x1880

 0x40A                             0x7003

 0x40B                            

 0x40C

 0x423                             0x03F3

 0x424                             0x1000

 0x431                             0x0200

 0x43B                            0x1002

 0x43C                            0x0029

 0x43E                            0x0929

 0x10A                            0x83B0

 0x10C                           0x2422

 0x10D                           0x8300

 0x10F                           0x1F83

 0x11C                           0x0000

 0x11E                           0x71C7

 0x11F                           0xC71C

 0x120                           0x3C71

 0x124                           0x0020

 0x125                           0x6300

 0x127                           0x2124

 0x128                           0x0100

 0x130                           0x0000

 0x132                           0x0800

 0x146                           0x0044

 0x147                           0x190A

 0x148                           0x31C3

 0x14A                           0xFF03

 0x14B                          0x1300

 0x14C                          0x1307

 0x14D                          0x0101

 0x14E                          0x0F4F

 0x14F                          0x1CC1

 0x150                          0x0000

 0x151                          0x00FF

 0x152                          0x00FF

 0x15C                         0x0003

 0x15F                         0x3210

 0x160                         0x5764

The Problems:

1. We read register  0x64 to 0x6D ,the result as below(DACLANE0_Error ~ DACLANE7_Error)

 DACLANE0_Error ~ DACLANE7_Error=0x2000

 DACLANE2_Error =0x2008

2.The JESD204B Link chain between DAC and FPGA is  always attemping to establish

  • hello,Jim

                   I added two registers(0x40B and  0x40C) values

     address                            data

     0x40B                             0x0064     

     0x40C                             0x2702

  • Guru 51130 points

    In reply to Wong:

    7200_LMFS_8212_Int_6X.cfgUser,

    The config file I used for your setup is attached. I am not seeing the errors you are reporting. What value are you using for K and what is your RBD setting?

    Regards,

    Jim

  • In reply to jim s:

    Hello,Jim

             Thanks for your help,

           The value K and RBD in my design: K=20,RBD=19

    Best Regards

  • Guru 51130 points

    In reply to Wong:

    User,

    See if this document helps.

    Regards,

    Jim

     Board trouble-shooting tips.docx

  • In reply to jim s:

    Hello, Jim

             Thanks for your patient help,I will try it later

    Best Regards

  • In reply to Wong:

    hello,Jim

         

    1. We read register  0x64 to 0x6D ,the result sitll has errors ,It shown as below(DACLANE0_Error ~ DACLANE7_Error)

     DACLANE0_Error ~ DACLANE7_Error=0x2000

     DACLANE2_Error =0x2008

    DACLANE0_Error ~ DACLANE7_Error=0x2000

     DACLANE2_Error =0x2008

    2.The JESD204B Link chain between DAC and FPGA is  always attemping to establish

    My design is attached:

    DAC_38rf82.cfg

  • Guru 51130 points

    In reply to Wong:

    User,

    Were you able to pass the NCO SYSREF test? What are you using for a clock source and SYSREF source? Are they from the same source?

    Regards,

    Jim

  • In reply to jim s:

    hello,Jim 

             Thanks for your help

    1.our test detais:

    (1) After power is applied and external reset is pulsed from low to high, bits [15:10] of 0x7F are 100000;

    (2) We enable LANE0 to LANE7,register 0x14A=0xFF03 ;

    we set NCO frequency 50MHz, register value : 0x11E=0xC71C,0x11F=0x1C71,0x120=0x01C7;

    Setting address 0x27 in page 1 to use SYSREF as the SYNC source;0x127=0x2828;

     

    If SYSREF is present:

                   LANE0 to LANE7 has no signal;the DAC output will be a stable 50MHz

       

    If SYSREF is disable:

                   LANE0 to LANE7 has no signal;the DAC output will be many tones:

    Pardon, I don't quite understand what is"NCO ONLY MODE".

    2.our clock tree is as below:

    (1) The chip HMC7044 generate reference clk and sysref to chip LMX2592 ,DAC38RF82, FPGA.

    (2)All output clocks of  Chip HMC7044 have the same phase .

    (3) HMC7044 Provide LMX2592_RefClk_120M to LMX2592 to generate synchronized clk Dev_Clk 7200M to DAC as DACCLK.

    (4) In my opinon , LMX2592_RefClk_120M and sysref_10M is synchronized, Dev_Clk 7200M is deterministic with the sysref_10M.

  • Guru 51130 points

    In reply to Wong:

    User,

    In NCO only mode, the JESD204B data is not used. This is good test mode to verify SYSREF is getting sampled properly by the DAC. For this test to be valid though, SYSREF cannot be a divide by 2 factor of the sample rate. For your test, please change SYSREF to something like 10.169MHz. With my LMK device, I used a divide by 177 instead of 180 for the test to create a fractional frequency. With this setting, if the SYSREF is getting sampled properly, the NCO output of the DAC will look like many frequencies. The reason for this is the NCO is being reset by the SYSREF, and this will cause the NCO frequency to keep changing to a different  frequency on every rising edge of SYSREF as SYSREF is not a integer divide down of the sample rate. If SYSREF is not received properly by the DAC, the NCO will not reset and the output will be a single frequency.

    Regards,

    Jim

  • In reply to jim s:

    hello,Jim

         Thanks for your help;Now I will describe our test details            

           (1)we change sysref from 10MHz to 10.169MHz,but it still exist errors,0x164~0x16c is 0x2000;

          (2)The SYNC signal is constantly from low to high;

          (3)We set NCO frequency 50MHz;We test NCO reset with sysref,when the sysref is present ;NCO output a single 50Mhz;

               In my opnion, DAC is not sample sysref ;We detect sysref is 10MHz , 900mV with oscilloscope;

     I don't know how to resolve this problem; please help me.

    Best Regards