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Part Number: DAC38RF82
we are testing DAC38RF82 now, we face some problems and need your help;
1.FDac(DACCLK)=7200M,External Diff Clk;
2.Single DAC(DAC A)
3. 1 IQ pairs
4. 8 serdes lanes
6.output IF analog signal=1.7GHz
9.FPGA GTH refclk=150MHz
Secondly,Our DAC38RF82 register configuration :
1. We read register 0x64 to 0x6D ,the result as below(DACLANE0_Error ~ DACLANE7_Error)
DACLANE0_Error ~ DACLANE7_Error=0x2000
2.The JESD204B Link chain between DAC and FPGA is always attemping to establish
I added two registers(0x40B and 0x40C) values
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In reply to Wong:
The config file I used for your setup is attached. I am not seeing the errors you are reporting. What value are you using for K and what is your RBD setting?
In reply to jim s:
Thanks for your help,
The value K and RBD in my design: K=20,RBD=19
See if this document helps.
Board trouble-shooting tips.docx
Thanks for your patient help,I will try it later
1. We read register 0x64 to 0x6D ,the result sitll has errors ,It shown as below(DACLANE0_Error ~ DACLANE7_Error)
DACLANE0_Error ~ DACLANE7_Error=0x2000
My design is attached:
Were you able to pass the NCO SYSREF test? What are you using for a clock source and SYSREF source? Are they from the same source?
Thanks for your help
1.our test detais:
(1) After power is applied and external reset is pulsed from low to high, bits [15:10] of 0x7F are 100000;
(2) We enable LANE0 to LANE7,register 0x14A=0xFF03 ;
we set NCO frequency 50MHz, register value : 0x11E=0xC71C,0x11F=0x1C71,0x120=0x01C7;
Setting address 0x27 in page 1 to use SYSREF as the SYNC source;0x127=0x2828;
If SYSREF is present:
LANE0 to LANE7 has no signal;the DAC output will be a stable 50MHz
If SYSREF is disable:
LANE0 to LANE7 has no signal;the DAC output will be many tones:
Pardon, I don't quite understand what is"NCO ONLY MODE".
2.our clock tree is as below:
(1) The chip HMC7044 generate reference clk and sysref to chip LMX2592 ,DAC38RF82, FPGA.
(2)All output clocks of Chip HMC7044 have the same phase .
(3) HMC7044 Provide LMX2592_RefClk_120M to LMX2592 to generate synchronized clk Dev_Clk 7200M to DAC as DACCLK.
(4) In my opinon , LMX2592_RefClk_120M and sysref_10M is synchronized, Dev_Clk 7200M is deterministic with the sysref_10M.
In NCO only mode, the JESD204B data is not used. This is good test mode to verify SYSREF is getting sampled properly by the DAC. For this test to be valid though, SYSREF cannot be a divide by 2 factor of the sample rate. For your test, please change SYSREF to something like 10.169MHz. With my LMK device, I used a divide by 177 instead of 180 for the test to create a fractional frequency. With this setting, if the SYSREF is getting sampled properly, the NCO output of the DAC will look like many frequencies. The reason for this is the NCO is being reset by the SYSREF, and this will cause the NCO frequency to keep changing to a different frequency on every rising edge of SYSREF as SYSREF is not a integer divide down of the sample rate. If SYSREF is not received properly by the DAC, the NCO will not reset and the output will be a single frequency.
Thanks for your help;Now I will describe our test details
(1)we change sysref from 10MHz to 10.169MHz,but it still exist errors,0x164~0x16c is 0x2000;
(2)The SYNC signal is constantly from low to high;
(3)We set NCO frequency 50MHz;We test NCO reset with sysref,when the sysref is present ;NCO output a single 50Mhz;
In my opnion, DAC is not sample sysref ;We detect sysref is 10MHz , 900mV with oscilloscope;
I don't know how to resolve this problem; please help me.
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