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Part Number: DAC38RF82
we are testing DAC38RF82 now, we face some problems and need your help;
1.FDac(DACCLK)=7200M,External Diff Clk;
2.Single DAC(DAC A)
3. 1 IQ pairs
4. 8 serdes lanes
6.output IF analog signal=1.7GHz
9.FPGA GTH refclk=150MHz
Secondly,Our DAC38RF82 register configuration :
1. We read register 0x64 to 0x6D ,the result as below(DACLANE0_Error ~ DACLANE7_Error)
DACLANE0_Error ~ DACLANE7_Error=0x2000
2.The JESD204B Link chain between DAC and FPGA is always attemping to establish
In reply to Wong:
SYSREF must be synchronized with DACCLK. I am not sure this is the case with your clocking tree. You must also meet setup and hold times for SYSREF, meet the common mode voltage of 0.5V if DC coupled, and have a swing of 800mV p-p. The SYNC will not be stable until the DAC registers SYSREF properly.
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In reply to jim s:
I'm sorry to trouble you again,
(1)We have test DAC38RF82 again.We set resgister 0x424=0x1800, Don't Bypass sysref alignment logic,Enable sysref alignment status outputs.
Reading resgister 0x05,the value is 0x0049;It means the sysrefphase3 state has been observed.
(2)we set NCO FTW= 0x006D3A06D3A0,fNCO=12MHz, SYSREF=10MHz;We also set 0x127=0x2828; 0x124= 0x0010;use all sysref to reset NCO;
when enable sysref ;NCO can be reset by sysref; As below
(2)BUT,when disable sysref ,there is no signal output;I don't what is wrong ?
I have duplicated everything mentioned above, and when I turn off SYSREF going to the DAC, I get a 12MHz clean output. How are you disabling SYSREF?you
Make sure you are not disabling the DACCLK as well.
From what I can tell about your results above, you are sampling SYSREF properly as long as every time you read register 0x05 (write a 0x0 first to clear it) you are getting the same sysrefphase state.
Thanks for your help ,Now I have solved the problem of NCO is reset by sysref;
In my opinion,NCO need reset signal to transit from Initialization state to normal operation state;Now ,I describe the details
(1) when enable sysref ;NCO can be reset by sysref; As below
(2) consequentially ,we use FPGA VIO module disable sysref ,NCO can't be reset by sysref,dac output 12MHz signal
Although,the sysref problem is solved,but,I have another question to need your help;
We read register 0x64 to 0x6B ,the result sitll has errors ,0x64 to 0x6B=0x2000;It means link configuration error;
register configueration attachment upload below
We change the Value of 0x14F from 0x1CC1 to 0x1C60;Then,we read register 0x64 to 0x6B ,the results has no errors.
The JESD204B Link chain between DAC and FPGA is established;
But, I don't known the reasons.
You set bit 5 = "1" which will cause the DAC not to report any errors that occur during the ILA sequence.
Thanks for your help; For ILA sequence errors,could you give me some advices to analysis the issues?
Today,I verifIed the ILA parameter S,M ,HD of My Xilinx JESD204B IP is equal the parameter of DAC38RF82; We set register 0x14E=0x0F4F;N’=16;N=16;HD=1;SCR=OFF;
But,DAC SYNC request for link configuration error.
Are you saying that you can get an output if you disable the ILA sequence checker but not if this is enabled? If this is the case, I have seen this issue with other customers as well. The problem is that the FPGA IP and DAC IP is not following the same methodology when determining how to set the ILA parameters. In some cases, an IP will set the parameter to a value that is the value -1, and in other cases the value used is as is. If this is the case, the ILA sequencer will always report an error. In most cases, customers ignore the ILA checker as long as valid data is achieved.
Thanks for your timely response,When I set bit 5 = "1" of 0x14F, The JESD204B Link chain between DAC and FPGA is always established,we can get an valid output data;
If I set set bit 5 = "0" of 0x14F, DAC SYNC always request for link configuration error and no output data。
Jim,could we bypass this problem?
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