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DAC81416EVM: SPI commands from a general SPI module

Part Number: DAC81416EVM
Other Parts Discussed in Thread: DAC81416, USB2ANY

Hi,

This may be a simple request.

I am having a hard time getting an output from the DAC81416 EVM.  I am using  a  NI8452 SPI Interface Module to control the DAC81416 EVM.  The documentation for the DAC81416 addresses  many different modes of operation but we simply need to program the device to produce DC voltage on three channels but not all at the same time.

Please tell me the sequence required to set the correct mode and how to address the registers required for a simple DC voltage out.

Thanks,

Pete Galaviz

  • Hi Pete,

    Welcome to E2E and thank you for your query. The steps are simple:

    1. Disable the device power-down bit

    2. Enable internal reference (on EVM the external reference is connected by default so this step is not needed)

    3. Select output range, if needed, By default, it is 0-5V

    4. Disable the power-down bit of the corresponding channel or channels

    5. Write the code to the DAC (make sure the SYNC_EN bit is in default mode)

    You can look at the applications information in the datasheet for the pseudocode examples.

    Hope that answers your question. Due to local holiday, I will not be available tomorrow. Please post you have further questions. I will get back on Monday.

    Regards,

    Uttam Sahu

    Applications Engineer, Precision DAC

  • Mr Sahu,

    Can you please provide more detailed instructions on how to address each register.  Not clear on how to do that.  Tthe documentation discusses an offset register but it is not clear what that means in terms of programming the required registers.  Ref: pg 31 of http://www.ti.com/lit/ds/slaseo0a/slaseo0a.pdf.

    Please provide exactly which registers need to be programmed and in which order.

    An example would be extremely helpful.

    Thanks,

    Pete Galaviz

     

  • Hi Pete,

    Apologies for the late response. You can look at page 48 of the datasheet. It provides the sequence of the register writes for a defined application. That would guide you for your application as well.

    Regards,

    Uttam

  • We need to talk to a real Eng. in the USA. Can you provide a phone number in the USA.

    Pete

  • Hello Pete,

    I assure you Uttam is a real Engineer, though he may not be located in the United States. At this point I do not see any reason that we need to escalate this to a phone call as all of this information is contained in the datasheet.

    Page 28 illustrates two tables which explain the bit-fields required for each a read and a write cycle. You will notice that in each case bits 21-16 are used for an address field. This is where to apply the "offset" values listed in the table on page 31. This is the current TI standard nomenclature for, essentially, register addresses.

    Page 48, which Uttam referred to, shows some example pseudocode for configuring the device.

    If you still find confusion on the matter, please let us know. Either myself or another real Engineer on my team will continue to support you.

  • We need a Phone number For USA  engineer.

    Peter

  • Hi Peter,

    I primarily support this part and I am located in India. So, I am the best person to have a phone call on this device. Having said that, we don't think you have an issue where a phone call would help at the moment. On E2E, we don't have chatbots, so everyone responding is a real human being and an expert on the corresponding part while there may be colleagues supporting during different timezones mostly to make sure our customers get answers in time.

    Let me provide more technical details so that that can get you started on the programming using your external SPI master. First of all, if it's the first time you are working with a DAC or SPI interface, it might be a good idea to use the EVM first with the USB2ANY adapter so that you can use the software GUI to program the DAC and also understand different modes practically.

    In case, you want to directly interface using the external hardware and software, let me provide more details that might help you configure the SPI interface and the DAC to get the desired output. Make sure you have connected the correct power supplies as specified in the EVM User's Guide. You would need VCC, VSS, VDD, and VIO. By default, the jumper settings (Table 5) on the EVM selects VIO from the digital interface connector J8. You need to change the jumper setting on J10 for providing the VIO using J7.

    SPI Configuration:

    SPI Mode: Mode 1

    SCLK Frequency: < 50MHz

    SPI Frame Size: 24-bit by default

    CS type: Active low per packet/frame

    Other digital pin configurations:

    /RESET should be HIGH

    /CLR should be HIGH

    /LDAC should be HIGH and then pulled-LOW after writing an SPI frame or after writing data to all DACs

    DAC configuration:

    The output voltage range of the DAC is set to 0-5V by default. If you want to change the settings to say, +/-5V, on DAC0, DAC1, and DAC2, then use the DACRANGE3 register and program the following data (I am writing in a pseudocode format for easy interpretation):

    WRITE DACRANGE3 (Addr: 0x0D), DATA(0x9999)

    Resulting SPI Frame: 0x0D9999

    The external reference voltage (2.5V) is connected to the DAC by default. The internal reference is disabled. for basic operation on the EVM, you can use the external reference. Reset bit 14 of the GENCONFIG register for enabling the internal reference. Make sure you disconnect the external reference from jumper J11 before you enable the internal reference.

    Next, bring the device out of power-down by resetting bit 5 in the SPICONFIG register as given below:

    WRITE DACPWDWN (Addr: 0x09), DATA(0xFFF8)

    Resulting SPI Frame: 0x09FFF8

    Next, set the SYNC-EN bits for the respective DAC channels and the LDAC bit to use the LDAC pin for simultaneous update. Note that this step is not required if simultaneous update is not required.

    WRITE SYNCCONFIG (Addr: 0x06), DATA(0x0007)

    Resulting SPI Frame: 0x060007

    WRITE TRIGGER (Addr: 0x0E), DATA(0x0010)

    Resulting SPI Frame: 0x0E0010

    Next, power-up the respective DAC channels using the DACPWDWN register:

    WRITE SPICONFIG (Addr: 0x03), DATA(0x0A84)

    Resulting SPI Frame: 0x030A84

    Next, program the required DAC code (example: 0xAAAA, 0xBBBB, 0xCCCC) in all the three DAC channels as given below:

    WRITE DAC0_DATA (Addr: 0x10), DATA(0xAAAA)

    Resulting SPI Frame: 0x10AAAA

    WRITE DAC1_DATA (Addr: 0x11), DATA(0xBBBB)

    Resulting SPI Frame: 0x11BBBB

    WRITE DAC2_DATA (Addr: 0x12), DATA(0xCCCC)

    Resulting SPI Frame: 0x12CCCC

    Assert the LDAC pin LOW and then HIGH here for simultaneously update.

    Hope that answers your question. Let me know if you face any issue. It's a good idea to upload a scope shot of the SPI frames in case you are facing any issue.

    I am writing down a few debug steps in case output is not available after programming:

    1. Check power supplies

    2. Check reference

    3. Check current drawn to know whether DAC is powered-on or not

    4. Check the SPI frame format

    5. Check the above sequence of programming. Cross-check the above values with datasheet in case I have some typos - I have tried to be as correct as possible

    6. Try without LDAC and see if there might be an update issue. Pull LDAC LOW in this case

    Regards,

    Uttam

     

  • Uttam

    Thanks for the information. 

    Peter

  • Peter,

    You're welcome. I am closing the thread from my side. In case you face further issues on this, you can reopen it within 60 days.

    Regards,

    Uttam

  • I have a few questions because I have not been able to get an output fron the DAC 81416.  I am trying to control the DAC 81416 with an National Instruments SPI module (NI-845x SPI).

    I used the DAC 81416 lower level software to set bits on the desired registered to configure the device to get output desired from the DAC.

    I then used that bit pattern from the NI SPI module.

    Is there any other thing I need to be aware of? The NI SPI module uses standard SPI protocol in regards to CS, CLK, and DATA.  I don't latch the data in with the LDAC line because it is also my understanding that the default mode is asynchronous.  Is that true? 

    Does the NI software generate anything else I need to be aware of.  

    Thanks for your help

  • One other thing, is there a set sequence to configure each register?

  • Hi Peter,

    Sorry for the delay in the response. It will be good if you could share some scope shots of the SPI pattern from your NI device. That way we can understand whether the pattern is correct or not. There is no other special requirement than what I have already mentioned in a previous post.

    Regards,

    Uttam

  • DAC PwrDown Register - 09 FF FE

    SPI Confg Register -  03 00 00

    Gen Confg Register – 04 00 00

    DAC0 Register 0D FF FF

    I leave all other registers in the default mode.

    One Question:

    From what I’ve read, the /LDAC is not needed because the default is asynchronous.  Is that true?

    Thanks again for your support,

    Pete

  • Pete,

    You are correct. For complete details, please see below.

    The LDAC pin is not required for using the device. As described on page 4 of the datasheet:

    Active low synchronization signal. When the LDAC pin is low, the DAC outputs of those channels configured in synchronous mode are updated simultaneously. Connect to VIO if unused.

    Later page 24 goes into further details concerning the register map:

    The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register and DAC output on a CS rising edge. In synchronous mode, writing to the DAC data register does not automatically update the DAC output. Instead the update occurs only after a trigger event. A DAC trigger signal is generated either through the LDAC bit or by the LDAC pin. The synchronous update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required between DAC output updates.

    The tables on page 38 describe the use of the SYNC-EN bits and the default values (0's) which correspond to asynchronous mode.