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Part Number: DAC121S101
We have this part providing 3.3V into a load that switches between 32k and 64k at 7kHz.
It performs perfectly for the first minute or so, but then the output drops to zero over a period of ~200ms. The output can recover if we rewrite a new value to the DAC, but then it will collapse again. No power cycling is required to do this.
Any ideas what could be going on here? Thank you!
Can you share a schematic of this? What does the power supply look like during the event? Does it collapse momentarily?
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In reply to Paul_Frost:
Here is a scope capture of the power supply (green) and the DAC output (light blue).
I have sent you the schematic snippets I have privately.
Let me know any suggestion you have or what else you might need.
In reply to Ryan.Bishop:
I do not see anything in the schematic that could be doing this, but notably, the DAC itself was not shown in the schematic you shared. What is the state of the sync pin during this time? Is it possible that there digital cross-talk in the SPI interface?
I will get the remainder of the schematic to you shortly.
We have checked the /SYNC pin and it remains high throughout the duration of the problem.
Update: The customer has wired a unity gain op amp buffer right on the output of the DAC and this resolves the problem.
Any reason why the DAC's output buffer wouldn't be able to drive a low current, but switching load like this?
Would it be possible to try replicating this loading on a DAC21S101 evaluation board?
I do not think this is necessarily an issue with the output buffer. My theory is that one of two things are happening:
1. The switching is causing glitches on the digital lines (specifically clock), causing the device to latch code 0x0000. Though the slow discharge makes me think the device is in power-down mode.
2. The load causing the supply to glitch, eventually causing a POR event.
I can see if I have an EVM to test this, but if it is one of these two issues, it would be hard to reproduce without the same layout, etc.
Given that the output buffer seems to fix the issue, then I think maybe theory 2 is a greater possibility.
Please try the following experiments:
My concern is that the shunt regulator circuit you shared only has about 22mA capability, so if there is anything else in the circuit that has a momentary draw we could collapsing the supply (albeit very briefly). The scope shot you shared had a pretty wide time-domain (40ms/div). Can you try monitoring the VDD supply with a scope that would trigger if the supply drops below ~3V with a scale of about 1us/div?
Also, we could try using an external supply to provide the VDD/REF voltage of the DAC and see if we can repeat the failure.
Are there other blocks that are powered by VDD3V3A and VDD3V3D?
Thanks for all your suggestions.
The customer is still waiting to try these, but their time has been pulled elsewhere.
I will close this thread for now.
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