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DAC38RF85: Minimum internal registers required to control the single NCO

Part Number: DAC38RF85

Hi Team,

We have a customer working on a project that only uses a single NCO portion of the DAC38RF85.
The question is, what are the minimum internal registers that are required to control this single NCO?

Thanks!

Jonathan

  • Jonathan,

    An example of what registers are written to enable the NCO is attached.

    Regards,

    Jim

    NCO_Only_Reg_settings.cfg

  • Thank you Jim and Jonathan. We will try the CFG file settings.

    Doug P.

  • The register values in your reply shows support for DUAL NCO operation. What changes/deletions if any, are necessary to only use the NCO/DAC (AB)?

    Also, the registers in were not listed in numerical order in the configuration file given as presented. Is there any restrictions on the order that these register values need to be sent?

    Is it correct to assume that once power is applied and the RESET! line is set high that the SPI register values you listed are all that is necessary to successfully bring up the single NCO output?

    I also have a single NCO only application hardware questions:

    In addition to power, ground, bias and bypass pins the only other pins that are connected are:

    1) Differential DAC CLK input

    2) SPI clock

    3) SPI data

    4) SDEN!

    5) RESET!

    6) Differential VOUT1

    Control lines that are tied off are:

    1) TRSTB is tied low

    2) TXENABLE is tied high

    All other inputs are left floating and unused outputs are not connected.

    Thank you for your support on the project

    Doug P.

  • Jonathan,

    After applying power, 9GHz diff clock, and a hard rest, if you load the following registers with the data in the attached file in the order present, you will get a 400MHz tone out of CHA only. TXENABLE should  be high and TRSTB should be low.

    Regards,

    Jim

    Diff_CLK_NCO_Only_Reg_settings.txt
    add	 data
    0x001 0x3080
    0x431 0x0000
    0x10C 0x2620
    0x119 0x0001
    0x11E 0x60B6
    0x11F 0xB60b
    0x120 0x0B60
    0x127 0x8888
    0x12F 0x0001
    0x128 0x0332
    0x128 0x0330
    

  • Guys

    We tried the configuration file that you sent for a single NCO.  No output was observed.  To help diagnose the problem here is our setup:

     

    1)      We are using the DAC38RF8x demo board in a standalone configuration to test our software driver.

    2)      The SPI jumpers have been removed.  Our micro controller is connected to the SPI header with the proper 1.8V logic voltage levels

    3)      R178 (RESETB) from the FTDI chip has been removed.  Reset is only done manually via the pushbutton switch.

    4)      The SPI data is being clocked in slowly at a 100 kHz clock rate

    5)      There is a 5 uS delay between the rising edge of the enable pulse and the start of the next byte being sent

    6)      After the page register is set, the enable line is set low and three 8 bit bytes (address, data, data) are sent MS Bit first and MS byte first.

    7)      The initial page register is set to zero, then is set to page 2 for address 0x431 and then set to 1 for all other transmissions

    8)      Since we are using an external clock that is single ended for the demo board, address 0x431 is set to 0x2000

    9)      The board is manually reset and then the 11 address/data sequence that you gave us is sent with the one exception noted above.

     

    Is it possible to accomplish what we want to do with this setup?

     

    Thanks

  • 2021.DAC38RF8xEVM-SCH_E.pdfAll,

    My EVM is setup for single-ended clock mode as well. Using the configuration file I sent with address 0x431 changed to 0x2000, after power up, I apply a hard reset using the FTDI device, load this config file and get a tone out on CHA.

    Can you read back the registers to verify you are writing to them properly?

    On the board, the reset can be controlled by either the switch or the FTDI device. I think the FTDI device is holding the reset high be default, preventing the switch from working. Please remove R178 (shown on sheet 7 of the attached schematic) and give this a try.

    Regards,

    Jim

  • Jim

    It is good to know that you are using the demo board like us.  I assume that you are also connecting via the SPI port (jumpers removed?).  In my previous message step 3 shows that I have removed R178.  Also Step 8 shows that I changed address 0x431 to 2000 just like you.

    Could there be an issue with the JTAG TRST?  My voltage level is about 400 mV.  Also, should I have the USB connection plugged in or not?  Perhaps the USB connection, which is not being used, is causing a problem?

    Or are you loading the config file you sent using the LOAD function of the GUI?

    thanks

  • Doug,

    just make sure JTAG RST (TRSTB) is connected to GND in regards to the JTAG port. I am using the GUI to load the config file. You should not need the USB connection plugged in. Can you verify that the reset is going low by probing R11 or C27 pad that is connected to the trace feeding the reset input? Are you able to do valid register read backs?

    Regards,

    Jim 

  • Jim

    I think we may be talking across each other.  I am not using the GUI at all.  The USB connector is not ever plugged in.  All I have is a microprocessor that has the SPI wires and ground connected between it and the demo board.  Our goal was to try to verify our schematic design as well as the code necessary to run a single NCO.  

    The approach was to power up the demo board, apply the DAC clock, do a push button reset (later to be controlled by the micro) and then load the configuration file totally from the SPI port.  Again, no input or controls from the GUI.  As you mentioned earlier, we also removed R178 so that the RESETB line was only controlled by the reset pushbutton.

    Since we are not getting any output I am concerned that there is some other signal on the demo board that is causing the problem.  I'll double check the TRSTB line.   

    Any others that should matter?

    thanks

  • Jim

    Some minor progress today.  I discovered that the TRSTB line did not have a good ground.  I now have some output.  However, the frequency is not correct.  In fact, it is always the same at .125 of the clock frequency.  Also, this 1/8 clock rate shows up after the 0x12F is sent and before the 0x128 address is sent twice.  It seems like it is some sort of test pattern.  When I change the clock rate by 2x the fraction stays the same.

    Just to be clear I send the page register three times.  The first time I set it to zero for the 0x001 address, and then it is set a second time to page 2 before the 0x431 address, and then just one more time before sending the remaining 9 bytes.

    Is that correct?

    thanks

  • Jim

    One more thing:  The last two lines of the configuration file you sent are:

    0x128 0x0332
    0x128 0x0330

    Shouldn't that be:

    0x128 0x0882
    0x128 0x0880

    thanks

  • Doug,

    No. This are not valid settings. Bytes 7:4 and 11:8 can only be either 0, 1, 2, or 3. 8 is not an option.

    Regards,

    Jim

  • Doug,

    This description is confusing. Please send all register address and data writes in the order you are writing them. Are you still trying to get only the NCO output, or are you now trying to get JESD data out?

    Regards,

    Jim

  • Jim

    Yes the description is quite confusing especially when compared to address 0x127 which also shows Bit 3 as the mem_SPI_sync.  The data for the register is 0x8888 which looks to be single bits.  Is the description for the 0x128 register just wrong?

    We are sending the exact values for the configuration file that you sent with the exception of address 0x431 which is (0x2000) for single ended clock.   Additionally, to start the SPI data stream register 9 is set to 0x0000 to select page zero, then after register 0x001 is sent the page register is then set to 0x0004, before 0x431 message is sent then finally, the page register is set to 0x0001 just once before the remaining 8 registers are sent.

    thanks

  • Doug,

    Sorry but I gave you the wrong info. The GUI is calculating these values incorrectly. If you plan on using mem_spi_sync, then the byte would be an "8" for these registers. The valid values should be 2, 4, or 8.

    The page writing mentioned above appears correct. Are you following section 9.1 for your start up procedure?

    Regards,

    Jim

  • Jim

    Once I changed the last two register addresses from 332/330 to 882/880 then I had total success.  I am now hopping between two frequencies.

    I also changed the sequence of register slightly.  Since we want to be able to randomly tune to any frequency in our range I moved register addresses 127 and 12F to before the NCO registers.

    This lets me change to a new frequency by only writing to the three NCO registers and then writing to register 128 twice.  I am a little concerned about the SPI clock speed as the data sheet says that the clock speed is 10 MHz nominal. At a 10 MHz clock rate  writing 120 bits, plus some overhead for the enable line takes 12 uS to just send the data.

    The data sheet shows that the 100nS clock  period is "nominal"  Is a 10 MHz clock a safe frequency to use?

    thanks

    Doug and team

  • Doug,

    Is this still an issue? If not I would like to close this post.

    Regards,

    Jim

  • Hi Jim,

    We're good. Thank you for the assistance.

    Regards,

    Doug