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Part Number: ADC12DJ3200
We are using ADC12DJ3200 in our design.
I have checked the eval board layout, and in layout Balun Negative side output is connected to ADC’s Positive side differential input.
Does this ADC have some internal circuitry which swaps the inputs internally that is if ADC’s P and N inputs are connected to balun’s N and P outputs respectively ,accidentally or intentionally , can we swap the P and N input internally through programming?
We are looking into this.
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In reply to jim s:
Please update on this.
In reply to LALIT VERMA:
The P and N swap was done to make the layout easier. But there is no way to un-swap it in the ADC with software.
In reply to Neeraj Gill:
As this ADC has two channels, and in eval layout for channel 1 balun output's P and N is connected to ADC inputs P and N but channel 2 balun output's P and N is connected to ADC inputs N and P.
Does this generate the inverted digital data like output data which should be 1 is 0 now and vice-versa.
Does we need to invert the data in FPGA?
If we invert the P and N connection of ADC input then do we need to invert data in FPGA.
Can you please update on this?
Can you please update whether we need to do something with the digital data in FPGA ,we obtained from ADC by swapping the P and N inputs of ADC with N and P outputs of Balun?
An early response will be highly appreciated.
Since P and N inputs are swapped on CHA vs CHB. The output data from CHA will be 180 degree out of phase from output of CHB if you care about the phase relation of CHA vs CHB. Please change the phase of CHB by 180 degree to allign the output data. If you don't care about the phase relationship between two channels then you don't have to do anything.
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