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ADC12DL3200: LVDS output interface synchronization?

user6100239
Prodigy 30 points
Part Number: ADC12DL3200
Other Parts Discussed in Thread: LMK04828

I use an ADC12DL3200 in a project. I choose to single sample and 4 LVDS outputs mode. ADC clock is provided by a LMK04828 at 1.2GHz, which also provide a clock of 300MHz to FPGA. In FPGA, I use 4 FIFOs to collect 4 LVDS path data with seperate path dclk, then read the FIFO data with 300MHz clock provided by LMK04828. However, these 4 path fifos' output data is not always aligned. I do not know where is the problem?

  • 0
    TI__Genius 12780 points

    Hi User,

    We are taking a closer look into this issue, and will get back with you soon.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 30 points

    Thanks, I found the 4 path dclks which would stop a while periodically at the moment when dstr is asserted. This is the reason that the Fifos' output cannot be aligned.

  • 0
    TI__Guru* 91947 points

    User

    What is generating dclk? Is this created from the 300MHz clock from the LMK? Are you not using the four output data clocks from the ADC? Are you using the strobes?

    What mode are you using, staggered or aligned? A timing block diagram may help us with helping you. What frequency are you using for SYSREF?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 30 points

    Hi Jim

    I find the main problem is that the strobe signals are not functional correctly when the sample frequency is higher than 200MHz in my design. The four output data clocks from the ADC would stop a while periodically is caused by the strobe signals are not functional correctly.

    ADC mode chosen is Single-Channel, 4-Bus, Aligned-Mode Timing (LDEMUX = 1, DES_EN = 1, LALIGNED = 1).

    I attached my design information in the word file (ADC12DL3200 Debug.docx) which contains schematic, FPGA design diagram and register information.

    Regards,

    LiangADC12DL3200 Debug.docx 

  • 0 in reply to user6100239
    TI__Guru* 91947 points

    Liang,

    When you mention "sample frequency is higher than 200MHz" are you referring to the CLK+/- inputs to the ADC? If so, the minimum frequency for this 800MHz.

    What range are you operating in? You cannot use this part at 200MHz.

    Regards,

    Jim 

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Liang,

    The design team thinks SYSREF timing may be the issue. Here are some suggestions to try:


    1. Bring up the system, to include enabling sysref.
    2. Clear the LVDS_STATUS register
    3. Monitor the LVDS_STATUS register to see if REALIGNED is getting set. If so, then the phase of sysref changed.

    If sysref is getting realigned, then try the following:
    1. Bring up the system, to include enabling sysref.
    2. Once sysref establishes the system reference, disable sysref processing Addr 0x29 bit 6 SYSREF_PROC_EN = 0
    3. Monitor the REALIGNED. Is it still getting set? Did the strobe problem go away?

    It is important to uses one of the sysref calibration methods provide. 
     
    If sysref is not the issue, see if you can capture the problem with a scope. Seeing a picture of the LVDS clocks and strobes could be useful.

    Regards,

    Jim