Other Parts Discussed in Thread: ADS1278
I have the ADS1278EVM on top of the modular motherboard (MMB0, Rev D).
I need to interface the EVM to an FPGA via J4 for control and J2 for the 8 serial data channels, using it in SPI mode, low-power mode, with 4.096 MHz input clock, 16.0 KSPS serial output (digital audio).
I would like to keep the EVM connected to the MMB0 thru all three headers (J3, J4, J5) for mechanical stability and to take advantage of the MMB0 power supply (J5), but otherwise use the EVM in standalone mode.
It looks like the analog input EVM/J3 pins (which go to MMB0/J10) are sufficiently isolated; i.e., not driven or loaded by the motherboard.
But I can't tell if the control pins on EVM J4 are sufficiently isolated (not driven by MMB0 J4) to directly connect my FPGA to EVM J4.
I have a Rev C. MMB0 schematic (could not find Rev D), which shows much of J4 being isolated by the FET switch U4 when U4/DCEN = 1, which I'm guessing is the default value unless an I2C write from the MMB0 processor changes it.
But I don't know if I can guarantee the processor won't eventually enable MMB0/U4, or if other pins on MMB0/J4 that aren't connected to MMB0/U4 are sufficiently isolated.
Note: I don't plan to use the ADC-Pro software in this configuration, or have the MMB0 processor do anything other than its normal background/idle stuff.
On EVM/J4, I need to drive
MODE[1:0] = "10" (pins 6,2), (but will omit these if it is safe to set non-default values on DIP switch S2).
FORMAT[2:0] = "010" (pins 14,12,8), (but will omit these if it is safe to set non-default values on DIP switch S2).
SYNCn = "1" (pin 1),
CLKSEL = "0" (pin 19),
CLK = 4.096 MHz (pin 17),
and receive
SCLK = 512 KHz (pin 3),
DRDYn = 16.0 KHz (pin 15).
I don't (think I) care about CLKR (pin 5), FSX (pin 7), FSR (pin 9), Dx (pin 11), DR (pin 13), SCL (pin 16), or SDA (pin 20) since I'm using SPI mode and not outputting the modulator clock.
THE QUESTIONS:
1. For the above scenario, do I need to completely isolate EVM/J4 from MMB0/J4 (e.g., clip the pins off MMB0/J4 so they don't conflict with my FPGA drive & receive)?
1a. If so, do we lose the pull-up resistors from MMB0 that keep the SCL & SDA pins from floating (as inputs to EVM U7, U8, and U14), and if so, would this be a problem?
2. Can I safely use the DIP switches on S2 for FORMAT[2:0] and MODE[1:0] instead of driving them with my FPGA?
3. Can I safely set the DIP switches on S1 to POWER-UP all 8 ADC channels? If the I2C port expanders are only reading these pins (never trying to write them), there should be no conflict.
4. The EVM-PDK User's Guide (SBAU197A–February 2012–Revised January 2016) in Section 5.6 (Power Supply Header, J5) states,
The ADS1278 digital supplies are connected as follows:
• IOVDD supply is connected to the +1.8VD pin of the J3 header.
• DVDD supply is connected to the +3.3VD pin of the J3 header.
Are the two bullets above backward? Everything on the EVM and MB schematics suggest a 1.8v core voltage (DVDD) and 3.3v I/O voltage (IOVDD); in particular, MMB0 (Rev. C) schematic shows
J5/7 = +1.8VD (EVM J5/7 = DVDD)
J5/9 = +3.3VD (EVM J5/9 = IOVDD)
Thanks very much!
