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Original question:

DAC3482: DAC3482 output signal spectrum have sideband

DAC3484: Frequency components other than generated in the NCO of DAC3484

Jade@lhs
Prodigy 100 points
Part Number: DAC3484
Other Parts Discussed in Thread: DAC3482

Hello,

We have a board where DAC3484 is connected to FPGA Virtex 6. We are feeding a 144Msps A and B channel data (IQ) to the DAC.

1. For the initial testing we have forced A channel to X"0000" and B channel to X"7000".

2. Interpolation set to x8

3. DAC  is running at 1152MHz (From internal PLL). PLL reference is 384MHz

4. NCO is enabled and NCO output frequency is varied from 144MHz to 216MHz.

5. We have observed the following behaviour. @191MHz of output (ie. NCO tuned at 191MHz), we observed lot of extra frequency components near 191MHz Carrier peak. But when NCO is tuned to 192MHz, this behaviour disappears and SFDR improves.

6. Spectrum is attached for different NCO outputs (see zipped folder).

What could be the reason behind this behaviour?

125.zip

  • 0
    TI__Guru 66044 points

    Hi Basil,

    These spurs could occur due to the NCO not being initialized. The NCO is basically a phase counter and requires synchronization to ensure the counting process is done correctly. Usually you will need to enable the on/off of the SIF_SYNC bit. Please refer to the DAC3482 initialization procedure for detail.

    I have checked if these are harmonics of the 191MHz folding back through aliasing, and these are not harmonics foldback.

  • 0 in reply to Kang Hsia
    Prodigy 100 points

    We followed same procedure as mentioned in DAC3482 initialization procedure. Even then same problem continues.

    Note that, we are only routing NCO output samples to DAC core (ie. Data input is forced to I = X"0000"  and Q channel to X="7000")

    So DAC is supposed to generate NCO carrier @191MHz without any spurious

  • 0 in reply to Jade@lhs
    Prodigy 100 points

    Can any one help me to resolve this issue.?

  • 0 in reply to Jade@lhs
    TI__Mastermind 18065 points

    Basil:

    When the spurs are present they are at offsets of 6 MHz or 12 MHz.  The 1152 MHz clock and the 368 MHz reference are a factor of 3.  The correlation is likely not a coincidence.  It looks like reference/clock/NCO are beating against each other.  This is not expected.  At 190 MHz I suspect the spurs line-up and are buried under the signal.  Just spit-balling here.  If you try with the TSW1400 board is there the same issue?  Maybe there is something unexpected with the FPGA platform interface.

    --RJH

  • 0 in reply to RJ Hopper
    Prodigy 100 points

    Hello RJH,

    We have done similar experiments by Just running DATA_CLK and forcing a constant value from the DAC (There is an option in DAC3484 to drive constant value to DAC by few register adjustment). Then we enabled the NCO to generate 190, 191, 192, 193...MHz carrier. Still the issue remains the same.

    By the way you have mentioned about "something unexpected with the FPGA platform interface".. Can you please expand this and tell me what all are the probable causes?