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ADC121S021: Behavior when SCLK idles low

1138
Expert 1226 points
Part Number: ADC121S021

Figure 1 "ADC121S021 Serial Timing Diagram" shows SCLK idling high; that is, it shows SCLK as already high when nCS goes low at the start of a data transfer, and it shows SCLK being brought high at the end of the data transfer prior to nCS being brought high.

We're interested in the behavior of the ADC121S021 when SCLK idles low, instead.

There is a mention in the data sheet that "If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK."  (Instead of the documented three zero bits at the start of a data transfer.)

How dependable is this behavior?  Can we expect that getting four zero bits is reliably and dependably the case when SCLK is low prior to and as we lower nCS?  Does this behavior depend upon any other conditions (such as how much time there is between when we lower nCS and when we raise SCLK for the first time)?

--thx

  • 0
    TI__Mastermind 24940 points

    Hello,

    The device does not act differently based on what state the clock is idle at. The images are using falling edges because the device clocks out data on the falling edges, this means that the receiving end will clock the input at the rising edges of SCLK.

    Because the falling edges is what the devise uses, and the rising edges is what the receiver uses, this leaves an unmatched (not equal) number of falling and rising edges when the first edge is a rising edge. In other words, the first edge after CS goes low is a rising edge; this means the receiver will clock in a leading zero before the ADC actually begins to output data which will be on the following falling edge.

    This is turn makes the receiver see 4 leading zeros instead of 3.

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Expert 1226 points

    Hello Cynthia,

    I believe in this scenario that that first leading bit (that we clock in as we raise SCLK for the first time) will be indeterminate if we were to read it in less than tEN=20ns after we lower nCS.

    As long as we do not violate that tEN constraint, is it guaranteed that that initial bit will be zero (of the total of four zero bits prior to us clocking in DB11), or is there any possibility that this leading bit (which was never "prepared" by the ADC seeing an SCLK falling edge) might not be zero?

    --thx

  • 0 in reply to 1138
    TI__Mastermind 24940 points

    Hello,

    Correct, the first unprepared leading bit will always be zero if following the time constraints.

    Regards

    Cynthia