ADC34J43: SYSREFP, SYSREFM, SYNCP~, SYNCM~ interface to LVDS

diverger

Expert 1175 points

Part Number: ADC34J43

I'm not sure how to interface LVDS to SYNC and SYSREF, the datasheet only gives specifications as below:

I have two questions:

Are these pins internally biased to 0.9V?
Are they compatible with LVDS?

over 4 years ago

0 dBrock over 4 years ago

TI__Genius 12780 points

Hi Diverger,

Yes, these signals are internally biased to 0.9V.

Yes, you can drive with LVDS.

Best Regards,

Dan

0 diverger over 4 years ago in reply to dBrock

Expert 1175 points

Thanks.

I'm a little more confused now. From the name, they should be differential inputs. Then what Vih and Vil stand for? And what's the differential threshold voltage?

0 dBrock over 4 years ago in reply to diverger

TI__Genius 12780 points

Hi Diverger,

Yes, they are differential inputs. Vih and Vil are the differential swing thresholds ((+) - (-)).

1.3V (Vih) to 0.5 (Vil) represents a max differential swing of 800 mV. This is enough range to support common interfaces like LVDS and LVPECL.

Best Regards,

Dan

0 diverger over 4 years ago in reply to dBrock

Expert 1175 points

You mean Vh (or Vl)= Vp - Vn? And when it is less than 0.5V, is recognized low, when great than 1.3V, recognized high?

Or 0.5 ~ 1.3 is just the common mode voltage range?

0 dBrock over 4 years ago in reply to diverger

TI__Genius 12780 points

Hi Diverger,

The Common Mode Voltage is internally biased to 0.9VDC. The differential swing around the common mode voltage is 1.3V (Max Vih)to 0.5V (Min Vil).

The EVM sets the common mode to 0.95V which is actually higher than the data sheet states, so I would actually just stay with 0.9VDC common mode voltage as the data sheet states.

Best Regards,

Dan

0 diverger over 4 years ago in reply to dBrock

Expert 1175 points

Sorry for so many question.

Then, what is the minimum threshold level for the differential voltage? For example, LVDS receiver had a Vth of 100mV.

0 dBrock over 4 years ago in reply to diverger

TI__Genius 12780 points

Hi Diverger,

The datasheet doesn't account for a minimum voltage swing for the SYNC. What FPGA will you be using?

Best Regards,

Dan

0 diverger over 4 years ago in reply to dBrock

Expert 1175 points

The planted one is Zynq Virtex-7 series, I'm planning to use it's LVDS driver built in, 1.8V or 2.5V one. So any suggestion?

0 dBrock over 4 years ago in reply to diverger

TI__Genius 12780 points

Hi Diverger,

I believe both 2.5 and 1.8V based LVDS still have the same common mode (1.25V) and differential swing (350 mV), so use which ever one is more convenient for your FPGA. On the ADC34J43EVM, I am able to establish the JESD link without the level shifting resistors, but would still suggest using them for long term use.

Best Regards,

Dan

0 diverger over 4 years ago in reply to dBrock

Expert 1175 points

Thanks for your help. I'll try that. Actually, I have tried to find a chip can translate standard LVDS to SLVDS, but with no luck.

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ADC34J43: SYSREFP, SYSREFM, SYNCP~, SYNCM~ interface to LVDS