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DAC900: how to avoid the zero drift of DAC900 output?

Part Number: DAC900

dear sir

    now l use DAC900 to achieve the current to voltage convertion, the schematic is as follow; the CH1 is the 5V_DAC, CH2 is DACB_CLK,CH3 is

test point TP8(test point up the R121), we can see the 5V_DAC is fine; when the fpga reset the DAC900E( write data to zero )with normal operation,The TP

8 voltage is detective to be about 0.5v after more than 50ms, what`s the problem ? when l change the FSA resistant R155 from 4.7k to 7.5k , FPGA reset

reset the data to zero, there is no bias voltage;   what`s the correct setting ? can you help me ?

 

  • Du,

    You need to provide at least one clock pulse rising edge to get the data latched into the device. I see no sign of a CLK on your circuit. The output will be unknown.

    Also, the load on both IOUT and /IOUT should be the same. This does not appear to be that way.

    Regards,

    Jim