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DAC39J84: JESD Interface SYNC problem

Prodigy 100 points

Replies: 6

Views: 160

Part Number: DAC39J84

Hi all,

I am trying to send data to  DAC39J84 from Ultrascale+ JESD block.
My design works fine with the evaluation board (http://www.ti.com/tool/DAC37J84EVM)

However, on the custom build board the SYNC signal from the DAC is not performing as expected.

My JESD design: subclass1, 8 lanes, F = 1, K = 20, Line rate = 6.25 GBPS, Reference clock = 156.25, Sysref = 4.88 (sysref is same for DAC & FPGA), DAC clk = 625 Mhz.

Again, the design works fine on the eval board and the layout of the custom board is very similar. I checked clocks and spi configuration of the DAC and clock distributor (LTC6951) they operate as expected and voltage levels are ok.

OUT1 -> DAC clk = 625MHz
OUT2 -> DAC SYSREF = 4.88Mhz
OUT3 -> FPGA Refclk = 156.25Mhz
OUT4 -> FPGA SYSREF = 4.88Mhz

This is what is happening on the eval board (top -> SYNC; bottom -> sysref):

On the custom board SYNC is always high and I am not sure what can cause that. Apparently, its a popular problem:


This is the flow:

1) Program clock distributor and align outputs (it supplies dac clk and FPGA clk; both SYSREF clocks are muted)
2) program FPGA
3) program DAC (here SYNC goes high and will never change)
4) supply SYSREF for ~ 1 sec (here SYNC pin should start toggling)
5) NOTE: JESD IP core can see the sysref as it assers tx_tready pin

Also, what does SYNC need to toggle? is it looking for SYSREF edge or K28.5 symbols?

Any ideas?

  • Guru 52415 points


    SYSREF = data rate / N*K, where N can be 1,2,3,ect...

    In your setup, SYSREF = 4.88MHz is not a valid frequency and the link will not get established. I suggest using 625M / (20 * 8) = 3.90625MHz.

    An invalid SYSREF frequency will cause SYNC to toggle.

    After you do the steps you mention above, you must initialize and rest the DAC to get SYNC to go low. See step #13 in section 8.3, Initialization Set Up, of the data sheet.



  • In reply to jim s:

    Hi Jim,

    Thanks for pointing that out. 

    I changed K to 32, so

    SYSREF = 625M / (32 * 4) = 4.88 MHz.

    I keep initialisation the same as before (as listed in section 8.3)

    1) Program clock distributor and align outputs (it supplies dac clk and FPGA clk; both SYSREF clocks are muted)
    2) program FPGA
    3) program DAC and init JESD link (here SYNCB goes low)
    4) supply continuous SYSREF pulses to DAC & FPGA and disable it after 1 sec. 

    SYNCB always stays low. Does it need to receive K28.5 symbols to go high?

    Error register 0x6c always produces 0xC003 (i clear it before reading.)

    My DAC config is attached.

    This is Xilinx JESD block configuraion (I am assuming that its ok, bacause it worked with the EVAL board)


  • Guru 52415 points

    In reply to Anton Gvozdev:


    I suggest you use Chipscope and monitor the data on all lanes along with SYSREF and SYNC. The DAC will hold SYNC low if it does not receive at least 4 consecutive K28.5 (0xBCBC) symbols on all lanes.




  • In reply to jim s:

    And in case of multiple SYSREF pulses the design will hang in the CGS phase until the SYSREF stops?

  • Guru 52415 points

    In reply to Anton Gvozdev:


    No. SYSREF is like a reset. It is used to reset the internal clocks. If it is the correct frequency, the clocks will be unchanged every time a SYSREF pulse occurs. This will not cause the CGS to change. See attached document for more info.



    1050.JESD204B Overview July_2018.pptx

  • In reply to jim s:

    The problem was caused by JESD PLL not locking and SYSREF being wrong.

    PLL didnt lock because the frequency generated by the clock distributor was off by 7MHz.