I'm having a difficult time with this DAC. I'm successfully sending data to what I believe is the DAC_A Data Register, yet there's no output. The chip is ACK'ing successfully as my master controller is returning successful transmission status for all data bytes.
The I2C bytes sent in master mode from my controller (100KHz clock) with DAC pin A0 connected to AGND:
Address = 0x48
Command = 0x08
Here's where your documentation gets sketchy (and it has errors as well IMHO)
Specifically the data sheet depicts DACA_DATA to be:
MSDB (b11:b8)
LSDB (b7:b2)
So, for my 8-bit 43608 DAC register (DATA[7:0]) what is the correct alignment within this bit field with an approxiamte half scale DAC output of ~50% (0x80)?
Table 5 says "MSB left aligned", but that could be interpreted as follows:
MSDB (b11) = DATA[7]
-OR-
MSDB (b9) = DATA[7]
I've tried aligning data in both positions and STILL NOTHING.
Just in case I am misconnecting pins, here's how I am current wiring the DAC:
!CLR = +5
VrefIN = +5
AGND = GND
VDD = +5
!LDAC = +5
A0 = GND
SCL = SCL (Photon D1)
SDA = SDA (Photon D0)
Scope or Logic Analyzer captures available if needed (and yes, the I2C lines are pulled up properly).
Sure hope you can assist getting this operational.
Thanks in advance.