Other Parts Discussed in Thread: ADS5400
The application i work on has very peculiar characteristics:
- Very low instantaneous bandwidth (like a sine);
- Input frequency range may vary, in steps, from 100MHz to few GHz
To this end many of the High Speed ADC portfolio can be used for it, both with LVDS output and with JESD204B.
For other reasons the sampling clock frequency will be set in the range 20 – 40 MHz.
Reading some High Speed ADCs datasheet the minimum sampling clock frequency (reported as nominal) is in the order of either 200 MHz (LVDS output) or 800 MHz (JESD204B output).
I understood that the JESD204B output HS-ADC have tight correlation between the JESD output bit rate and the sampling clock frequency.
Is it possible to use the much lower sampling clock frequencies (e.g. 40 MHz) with these High Speed ADCs with a low degradation in the ENOB?
Or are there other limitations in the ADCs core way of working?
