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ADS5295: Is it possible to synchronize two ADS5295 in two-wire mode?

Prodigy 40 points

Replies: 1

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Part Number: ADS5295

Hi.

We have two ADS5295 in two-wire mode with the same input clock. The frame clocks, generated by chips, are 1/2 of input clock. 

Often, after the start, these two ADCs are not synchronized - the second generates frame clock shifted by 180 degrees relative to the first.

Is it possible to achieve synchronous frame clock generation?

  • Kostantin, 

    Thanks for using the ADS5295!

    first of all, all ADS chips clock should be synchronized. then you can follow the datasheet decritpion of SYNC pin. you can put the device into the ramp pattern first for testing and make all chips ramp patterns are synchronized, 

    Thanks!

    SYNCHRONIZATION USING THE SYNC PIN
    The SYNC pin can be used to synchronize the data output from channels within the same chip or from channels
    across multiple chips when decimation filters are used with a reduced output data rate. When decimation filters
    are used (if the decimate-by-2 filter is enabled, for example), then effectively, the device outputs one digital code
    for every two analog input samples. If the SYNC pulse is not used, then the filters are not synchronized (even
    within a chip). When the filters are not synchronized, one channel may be transmitting codes corresponding to
    input samples N, N+1, and so on, while another channel may be transmitting codes corresponding to N+1, N+2,
    and so on.
    To achieve synchronization across multiple chips, the SYNC pulse must arrive at all ADS5295 chips at the same
    time (as shown in Figure 66). The ADS5295 generates an internal synchronization signal that resets the internal
    clock dividers used by the decimation filter. Using the SYNC signal in this way ensures that all channels output
    digital codes corresponding to the same set of input samples.
    Synchronizing the filters using the SYNC pin is enabled by default. No register bits are required to be written.
    The TP_HARD_SYNC register bit must be reset to '0' for this mode to function properly. As shown in Figure 66,
    the SYNC rising edge can be positioned anywhere within the window. SYNC width must be at least one clock
    cycle.
    In addition, SYNC can also be used to synchronize the RAMP test patterns across channels. In order to
    synchronize the test patterns, TP_HARD_SYNC must be set to '1'. Setting TP_HARD_SYNC to '1' actually
    disables the sync of the filters.