DAC7611: output is wrong

Prodigy 660 points

Replies: 15

Views: 144

Part Number: DAC7611


customer use DAC7611 in flow meter. and here is a question:

yellow is data, green is CLK, blue is LD

do you have any suggestions?


15 Replies

  • Hi Yuan,

    How is the output wrong? Is it not updating at all or are you seeing an incorrect value as intended? The data is latched on the rising edge of CLK, is that what you are intending?

    Are you using chip select?



  • In reply to Paul_Frost:

    1.the value is wrong,for example,the input data is 7D0,but DAC7611 output 765mV. the wave picture is  that  yuan attached.

    2.we set cs pin low.

  • In reply to Paul_Frost:

    I have tried to some datas, they are wrong,001(1mV),002(11mV),004(47mV),008(190),010(765mV),020(3064mV),040(0mV),0080(0mV),100(0mV),200(0mV),400(0mV),800(0mV),030(3831mV),038(4022mV),03C(4070mV),03E(4082mV),03F(4086mV)

  • In reply to Paul_Frost:

     please refer to the sch

  • In reply to Paul_Frost:

    what is the rising time of clk?

  • In reply to Paul_Frost:

    here is the clk waveform from customer.

    do you think it's correct?


    waiting for your reply.

  • In reply to Yuan Tan63:

    That transition is acceptable, assuming the data is valid during the transition.  100kΩ on the input pins is a bit high, as our IIL and IIH specification is 10µA max.  Can you also verify if your isolation stage is inverting your data? Also, please verify the voltage on VDD is correct.  What does LD look like after the data is written?



  • In reply to Paul_Frost:

    Hi Paul,

    Thanks for your reply. To make the question more clear, here I have a summary:

    customer use the SCH as I attached before with those changes: change optocoupler to HCPL-181-060E; remove 100k resistors.

    and he tested with different up-load resistor of optocoupler's output. (shown as R81 in SCH) here is the results:

    1 R81=2K, it works

    2 R81=5.6K, it cannot work.

    customer compared two clk waveforms, he found the gap between two trising is around 15us.

    so here is the questions:

    1 Is clk rising/falling time the real reason for the two different results?

    2 if yes, how clk influence? what's the definition and  recommeded range for this spec?

    for definition, we feel confused with the description as below, here seems a conflict between "10%~90% of +5V" and "1.6V",

    and for recommended range, I don't find words from datasheet.

    3 do you know the reason behind that? why rising/falling time influence that?

    paul, the first 2 questions are more important, customer want to confirm that, and for 3, if you know the answer, it's nice.

    thank you again.


  • In reply to Yuan Tan63:

    Hi Yuan,

    1. I do think the rise and fall time alone is the problem, but rather that the edge timing is causing the data to be misformatted.  The isolator's datasheet shows that the tRISE and tFALL time for ~5kΩ is ~100µs.  I am concerned that the data as shown in the first image is not valid with those edge transitions.  Please collect another image, similar to the one below but measured directly at the DAC pins.



  • In reply to Paul_Frost:

    "I am concerned that the data as shown in the first image is not valid with those edge transitions."

    reply: I'm sure the data is valid with those edge transitions,because the data is Stable ,"0"(0V)or “1”(5V) ,when the clk changed from 0 to 1 and  the data keep enough time accordind with the datasheet .

    "Please collect another image, similar to the one below but measured directly at the DAC pins."

    reply:The waves of you see all the pictures are measured directly at the DAC pins.

    1R81=5.6K, it cannot work. the dats as below:

    0V-5V    tr=41uS,

    LD: tLD1=135uS>15nS


    SDI:tCl=129.8uS>30nS   tCH=209uS>30nS

    tDS=129.8uS>15nS   tDH=209uS>15nS

    2 R81=2K, it works the dats as below:

    0V-5.0V    tr=19uS

    LD: tLD1=126uS>15nS


    SDI:tCl=113.0uS>30nS   tCH=227uS>30nS

    tDS=113.0uS>15nS   tDH=227uS>15nS.