Hi,

Thanks for using ADS52J65EVM.

We will reply your question very soon.

Thank you!

Best regards,

Chen

Hi,

Is there difference between hardware RESET pin and SOFTWARE_RESET bit in register 0x0h?

Just note for external SPI programming. User should mount R116 for disabling output of U14 (ISO7141CCDBQR). Otherwise there is a conflict for LMK_CS signal.

Regards,

Daniel

Hi,

The hardware RESET is easy for you to concern about the timing.

The software_RESET (using register) will reply on your signal speed.

both will reset all the registers to the default mode.

we will reply more questions to you!

Thank you!

Best regards,

Chen

Hi Chen,

Thank you very much.

We have just finished the integration of EVM board into our fpga platform. Everything works fine. Next week we will continue in evaluation and modification of the board (mentioned in another thread).

Thanks.

Best Regards,

Daniel

Hello,

Does ADS52J65 require a SYSREF event or specific logic level even when subclass 0 is used?

I'm trying to run LMK04821 in distributed mode. I have removed jumpers J6, J7, J8, J11, connected ultra-low phase noise sinus clock source to J9. LMK was reconfigured to distributed mode with SDCLK outputs powered down. Both ADc and FPGA see correct clock from LMK04821 but problem is that the ADS52J65 refuses to start complete JESD communication. Sometimes some lanes report receiving K28.5 with completed CGS but not all. When I switch back to dual PLL configuration (original register sequence from EVM) everything works fine.

Please do you have any advice for me?

Best regards,

Daniel

Hi,

Thank you!

Yes, we will repeat your question on our side.

We will let you know soon.

Thank you again!

Best regards,

Chen

Hi Chen,

I took original script for dual PLL configuration with SYSREF pulses and modified it for distribution mode. Then the ADS52J65 started sending data. It seems even with JESD_SUBCLASS bits (reg 0x34) set to 0 the ADc needs SYSREF. Or maybe I overlooked something.

Anyway...I'm facing problem with worse SNR performance because of increased noise floor when LMK is used in distributed mode. The clock source has much better phase noise than used Crystek VCXO. I will ask a question about this in the clock forum.

Best regards,

Daniel

Hi,

Here is the reply from the system engineer for your question:

Thank you!

===============

Subclass mode 0 and 1 need sysref and sync 

Subclass 2 needs no sysref 

===============

Thank you!

Best regards,

Chen

Hello,

since we are playing with modification of analog front-end we are facing issues with the ADc. The modification includes replacing two analog channels with transformes with higher ratio and increasing differntial resistors to 540ohm (2x270ohm).

It seems the ADS52J65 consist some internal funcionality what forces the ADc to be stucked - SPI, JESD204 communications works but the ADc doesn't send data.

We observe that the Vcm has value 900mV even when it is set to 750mV or 850mV. The JESD204B receiver has asserted (active) SYNC and sees CGS and K28.5. But the start of data and ILA is not detected. We suppose the internal block with sampling circuit and ADc core resist to work for some reason in relation to mentioned front-end modification.

Also another thing to mention is when we placed parallel inductance at the input (for impedance matching) the problem was same (Vcm 900mV, JESD204 tranceiver not sending data). We supposed the ADc doesn't like short-circuit through DC coupled inductor so we added capacitors for AC coupling. After that the ADc started to send data and Vcm dropped to the programmed value.

So is neccessary to have all inputs with same analog front-end? For example could the ADc have problem when one analog input consist default differental 50ohm resistors and next one has 540ohm (problem with bias)?

Is possible somehow to force ADS52J65 to send the data (start sampling) when it is stucked in the state mentioned above?

Is possible somehow to generate internally SYSREF signal without on-board LMK04821 usage?

Thanks

Best regards,

Daniel

Hi,

Thank you!

Yes, we will repeat your question on our side.

Thank you again!

Best regards,

Chen

Hi,

When using ADS52J65 device for all the Vcm pins (for different signals), please refer to the data sheet

page 7 (for Vin_CM=0.75Vdc) and (for Vclk_CM=1Vdc)

and page 11 (for SYNC~ and SYSREF both Vcm=1.2V) and (for CML output Vocm=0.45V)

Please make sure you have the same Vcm for all their different pins.

Also please refer to page 125 Figure 159 as well.

Also for related to LMK, please refer to the data sheet page 124

and you can see how to connect LMK to ADS52J65 and to your FPGA board together.

Thank you!

Best regards,

Chen

Hi,

thanks.

Well we will modify all analog inputs same way and see what happens.

I have question about the ADC clock input. We have bypassed LMK and directly connected 1.8V CMOS clock to ADC clock input as shown in Figure 160 page 126. The SNR performance is much better because of much better phase noise performance of used clock source (sinus 10dBm/2Vpp).

We would like to feed ADC clock input without CMOS translator but we are unsure about clocking scheme for single-ended sine-wave clock source. Datasheet specifies that ADc can handle differential ac-coupled sine-wave 2Vpp but it is not clear how to connect single-ended sine-wave clock. We suppose the CLKM should be AC-coupled to GND and CLKP connected to 2Vpp clock source (with AC coupling). Behaviour of the clock buffer auto-detect  feature is unclear for this case.

Can you please your system engineer about this?

Thanks

Best regards,

Daniel

Hi,

Thank you!

from this ADS52J65EVM board design,

it looks like the ADC clock input only is connected to LMK only.

so I don't know if the device can be working fine or not (with your bypassing LMK)?

Also please refer to the datasheet page 30 figure 62 and page 126 figure 160,

when you are connecting CLKP pin to your CMOS (from 0V to 1.8V) clock input,

please don't let it run from -0.9V to 0.9V.

Thank you!

Best regards,

Chen

Hi Chen,

The reason is evaluation of ADS52J65s limits.

EVM board has ADC clock only via LMK and we miss option directly clocking the ADc. We had  a problem with phase noise performance when LMK is used in distributed mode. This is known problem what is discussed in clock group. That's the reason why we bypassed LMK by removing C175/C176, powering down the 1_LMK_ADC_CLKP/M and connecting our CMOS buffer directly into ADc clock pins without AC-coupling (the CLKM pin was directly grounded). The device works fine and as I said the SNR performance significantly increased so the ADS52J65 can have benefit from better clock with much better phase noise. If you or your colleagues are interested I can give you more details by e-mail (proprietary reasons).

Our CMOS buffer has additive jitter and degrades phase noise of original clock source what we would like to evaluate directly to ADC clock input. I suppose we need to activate internal VCM 1V so that our AC-coupled single-ended clock source (from -1V to 1V) will swing from 0V to 2V. We are unsure about auto-detect feature of internal clock buffer so that's the reason why we ask.

We suggests to have CLKM ac-coupled to GND and CLKP ac-coupled to sine-wave clock source with 50ohm termination. How we do it is our problem. What do you think?

Best regards,

Daniel