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ADC12DJ3200: JESD204B configurations

Expert 1110 points

Replies: 19

Views: 225

Part Number: ADC12DJ3200


I start looking into the "slac748_adc12dj3200_A10fpga_jesd204b_from_TI", the source code and user guide etc. 

I noticed that the JESD204B configuration seems different between user guide and the source files, in which the source file are restored with Quartus Prime Pro version 16.1.

For example, it shows K= 4 in the user guide for configuring ADC but the K = 32 in "altera_jesd2041_.... v", see below. The values below matched with QSYS setting. 

altera_jesd2041_altera_jesd204_161_kzbcg4i #(
.DEVICE_FAMILY ("Arria 10"),
.L (8),
.M (4),
.F (1),
.N (16),
.N_PRIME (16),
.S (1),
.K (32),
.SCR (1),
.CS (0),
.CF (0),
.HD (0),
.ECC_EN (1),
.DLB_TEST (0),

My questions are:

Q#1, should K =32 or K=4 be used? Also other parameters if differed. 

Also, in the user guide, it states "In this EVM revision P & N pins of upper four SERDES lanes are swapped, hence Rx lane polarity inversion is implemented in the design to address that." So,

Q#2, which FPGA module or block address it. 

Hope to hear from ASAP.

  • New2Day:

    There may be some flexibility to setting the K value dependent on your HW and FPGA.  Typically this value must be optimized for a given system.  That may explain the difference between a TI set-up with TI capture solution vs other HW and FPGA capture solution.

    The swapping of the pins may be referencing settings in the ini file to invert the proper pins.  I will defer this post to the ADC12DJ3200 expert to confirm and expand on my explanations.


  • In reply to RJ Hopper:



    As shown in my post(highlighted), besides K, N/N', S and F are not same neither.

    I'm guessing it's due to use version 16.1 Quartus Prime Pro and Arraia 10 SoC FPGA so IP core were updated. 

    So I like to confirm all parameters should be matched with values set inside ADC device. 


    I have put following signals onto Signal Tap and observations:

    rx_link_clk_rstn   = LOW

    pll_locked = HIGH

    serdes_data_in = all '0'

    serdes_data_valid = all '0'

    rx_ready = HIGH

    rx_is_lockedtodata = LOW

    in which, rx_link_clk_rstn is LOW is due to rx_is_lockedtodata are LOW. rx_is_lockedtodata are LOW may be due to serdes_data_in not BCBDBC. . ..

    I like to get your opinion why serdes_data_in are not BCBCBC. . and or rx_is_lockedtodata are LOW. 

    Thank you.


  • In reply to new2day:


    I am going to take a look at the design and will let you know by 01/22.



  • In reply to Neeraj Gill:

    Thanks a lot. 

    I found and changed the code that set upper lane[7:4] to be non-inverted. 

    For the link-up and aligned issue (rx_is_lockedtodata are LOW), hope to hear from you ASAP. Thank you very much. 

  • In reply to Neeraj Gill:


    Any updates? Hope to hear from you ASAP. Thanks.

  • In reply to new2day:


    Here are few things I would like you to try.

    1. Make sure the ADC is getting the proper clock and enough current(3A) and is getting programmed properly. You can try to write a value to the ADC and read the value back and make sure it is as expected.

    2. Make sure the SYNC pin from the FPGA routed to ADC SYNCSE pin.

    3. You can force the ADC into CGS mode by doing a software sync. Here are instruction below.

    a. Disable JESD BLOCK by clicking the JESD block enable button.

    b. Click the JSYNC_N sysnc Request.

    c . SYNC input Selection select no SYNC input Signal

    d Enable the JESD block back.


  • In reply to Neeraj Gill:


    I'm not using the EVM but our own board. I'm using the "ARRIA 10 JESD REFERENCE DESIGN" from TI. 

    I have tried all things mentioned above and more:

    1. I have no problem write and read ADC registers and clock is 3GHz @ 3dBm from Sig Gen

    2. Yes, SYNC pin is connected to FPGA and FPGA will issue a SYNC to ADC once the rx_is_lockedtodata signals go HIGH from JESD204B receiver (PHY)

    the problem I'm having is that rx_is_lockedtodata signals didn't go HIGH and there are no "BCBCBC.." on serdes_data_in bus. See attached signal tap screenshot. 

    of cause FPGA won't issue a SYNC and register 0x208 of the ADC is 0x4.

    I'm waiting for the insight or answers or ideas why.  ASAP please. 

    About SYNC by register 0x203 after disable JESD block and then setting  0x204 to 0xA, the register 0x208 changed from 0x4 to to 0x64. 

    However, nothing changed on two signals(buses) mentioned above. 


  • In reply to new2day:


    It sounds like the FGPA is not getting proper reference clock and hence it is not able to get the lock on serdes) can you please make sure the proper refence clock is getting to the FGPA.



  • In reply to Neeraj Gill:

    1. FPGA DEVCLK is 300MHz and ADC sampling clock is 3GHz. SYSREF to both FPGA and ADC are 3GHz/640 while mgmt clock is 100MHz.

    The screenshot of signal Tap attached in last email is running at 300MHz, in which mgmt clock and SYSREF are in it. 

    2. I've also tried recompile the FPGA project to run at lower rate as below but again no luck.

    FPGA DEVCLK = 125MH and ADC is sampling at 1.25GHz

    Thank you.

  • In reply to new2day:


    I am going to talk to our firmware team and see if we can solve your issue. In the mean time can you make sure if the ADC eval board is getting 5V and at minimum 3A of current.