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ADC12DJ3200: Initialization Set Up repeatability issue

Part Number: ADC12DJ3200

Hello,

I am seeing an issue with calibration repeatability with the Initialization Set Up. I am configuring the ADC for JMODE0 and sampling a CW signal. If I repeat the Initialization Set Up, I see a 6 dBm amplitude variation on the sampled signal. I am using the following Initialization:

adc.write(0x200, 0x00); // clear JESD_EN - Always clear JESD_EN before clearing CAL_EN
adc.write(0x061, 0x00); // clear CAL_EN
adc.write(0x201, 0x00); // set JMODE0
adc.write(0x062, 0x01); // CAL_CFG: FG

adc.write(0x061, 0x01); // set CAL_EN - Always set CAL_EN before setting JESD_EN
adc.write(0x200, 0x01); // set JESD_EN

adc.write(0x2B0, 0x00); // turn off sysref cal
adc.write(0x06c, 0x00);
adc.write(0x06c, 0x01); //trigger ADC FG calibration
// Wait for FG Calibration to complete by monitoring 0x06a bit 0

// Calibrate sysref
adc.write(0x2B1, 0x05); // config the cal
adc.write(0x2B0, 0x01); // start sysref cal


// Wait for sysref calibration to complete by monitoring 0x2B4 bit 1

If I re-run the above steps, I will see one of two possible amplitudes on my sampled signal. I would appreciate any suggestions on what might be happening. Thank you.

  • Hi Jaun,

    Can you please add following in beginning of your register writes. 

    adc.write(0x000, 0xB0); // Soft reset of chip 

    sleep(1us) //wait for 1 usec.

    adc.read(0x270) / Read continuously until bit 0 returns 1 to indicate initialization is done

    This will make sure the ADC is getting initialized properly. 

    Also I would also recommend you follow the initialization setup procedure (section 8.3 of the datasheet)

    Regards,

    Neeraj 

  • Hello Neeraj,

       Thank you for the response. I added your suggestions to my ADC initialization. Note that 0x270 is not in the datasheet but I monitored until bit 0 returned a 1 as you suggested. Unfortunately it did not resolve my issue. 

       I believe I am following the initialization setup procedure from section 8.3 in my initialization code above. Do you have any other suggestions? Thank you for your help.

  • Hi Jaun,

    Can you please send me the screen shot of the FFT when you see the issue and when you don't see the issue. Basically what I am try to look for is the noise floor also getting affected for only the input signal is changing amplitude?

    Regards,

    Neeraj 

  • Hello Neeraj,

       The noise floor is also getting affected. I captured the ADC samples in the FPGA and imported into Matlab. Here is the FFT plot.

  • Hi Jaun,

    Can you please try the following register writes and see if fixes your issue? Please note here I am using KM1 value as 3 you might have to update KM1 value according your use case. 

    0x0000 0xB0 // Do soft reset
    0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
    0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
    0x0201 0x00 // Set JMODE0
    0x0202 0x03 // Set KM1=3 so K=4
    0x0204 0x01 // Use SYNCSE input, offset binary data, scrambler enabled
    0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
    0x0048 0x03 // Set serializer pre-emphasis to 3
    0x0061 0x01 // Set CAL_EN (always before JESD_EN)
    0x0200 0x01 // Set JESD_EN (always after CAL_EN)
    0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
    0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

    Regards,

    Neeraj 

  • Hello Neeraj,

        Thank you for the followup suggestions. I had to regenerate my JESD204 cores to enable descrambling. I have added the additional setup commands as you have suggested above. 

    Unfortunately I am still observing the same issue.

    FYI, my register values are the same as your above except for 0x0202, which is 0x1F in my case, and 0x204 which is I set to 0x3 (Signed 2’s complement, scrambler enabled).

    I would appreciate any additional suggestions. Thank you,

      Juan

  • Hi Juan,

    Can you try to following register writes.

    0x31 0xA0 // Set the Full scale of ADC to 800mV default

    0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
    0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

    lets see if you get the same results?

    Regards,

    Neeraj

     

  • Hi Neeraj,

       The datasheet states 0xA000: 800 mVpp (default). It should be the default value but I explicitly added the commands prior to triggering calibration:

    0x30 0x00 // Set the Full scale of ADC to 800mV default
    0x31 0xA0 // Set the Full scale of ADC to 800mV default

    0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
    0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

    I get the same results; no improvement.

  • Hi Juan,

    Can you please try using coherent frequency when you do the FFT?

    Regards,

    Neeraj

  • Hi Neeraj,

       I want to thank you for your help and suggestions. I believe I have my issue fixed.

    The problem ended up being with my JESD204 RX Core in the FPGA. Specifically with the timing of the SYNCSE signal going from the core to the ADC. My ADC calibration function was also resetting the JESD core. I found that simply resetting the core would induce the problem (a reset will pulse the SYNCSE signal). In debugging the SYNC, the issue resolved itself so I added timing constraints on the SYNC as the final solution.

    Thank you again for your help.