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DAC088S085: can't make Dout work

Part Number: DAC088S085

to whom it may concern,

I'm trying to daisychain two DAC088S085, but I can't make Dout of the first one to output any signal, while I can control the analog outputs of the first DAC cprrectly, I'm not sure why the Dout won't respond. Right now, I'm using the TSSOP package. Couple of months ago I used the WQFN and at some point I was able to make Dout work, so I believe the code I'm using is correct. In the pictures below you can see the nSYNC (ch2), SCLK (ch3) and Din (ch4). As explained on the manual, I'm sending 32 falling edges of SCLK, with nSYNC pulled down throughout. The Din code is 11000110 01100000 11000110 01100000 which would be broadcast to all channels the value 0x66 which is 2V with Vref1, Vref2 at 5V. In this case I would expect Dout to be 00000000 00000010 11000110 01100000 since in the manual it says the 15th cycle is high, but nothing comes out. Any information could help as I'm running out of udeas

Note in the picture the amplitudes of all signals are halved because all the channels on the scope have 50ohm plugs.

  • Jacopo,

    Can you make another measurement for us that includes the DOUT (or SDO) line? Looks like 1us / div on your scope settings so you're probably not violating the 30MHz SCLK limitation of the daisy-chain SPI but it is kind of hard to tell with this level of resolution. It is also a bit difficult to say what the SCLK phase and polarity settings are from this view, so another capture zoomed in on the SCLK edge relative to an SDI edge would be helpful as well.

    If you can provide some of these additional captures maybe we can find more clues concerning what is going on.

    Are you using the EVM or some custom hardware?

  • hi Kevin,

    thank you for your quick reply. Sorry I forgot to mention those information: clock rate 14MHz, SPIMODE1, MSBFIRST. The master is an arduino nano. The picture is a zoom in of the first 8 bits sending the code 11000110 (you can see on ch2 nSYNC turning low), no output on Dout

  • Jacopo,

    The daisy-chain functionality of this device is fairly straight forward so I feel like there is something else happening here beneath the surface that I haven't seen yet via the forum thread. Could you identify whether you're using the EVM or not and/or share a schematic for your design if it is your own hardware?

    A very brute-force test I would maybe suggest is just writing all 1's (or just tie to to logic high) to the first DAC and providing an indefinite volume of SCLKs and see if anything happens on SDO. If you don't see anything then I feel like we're looking at some kind of board / SCH level issue. Maybe try probing directly at the SDO pin as opposed to any other board-level connections.