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ADS54J60EVM: Operation of the demo board with external CLK

Gruffalo
Intellectual 280 points
Part Number: ADS54J60EVM
Other Parts Discussed in Thread: ADS54J60, LMK04828

Hi,

I am trying to run the ADS54J60-EVM with an external CLK which should span from min (~250 Msps) till max (~ 1Gsps). Here is what has been done so far:

a. modified the HW -.> removed C65,C73 and placed 0.1uF on C64 and C72 instead

b. feed into J6 the 10 MHz ref from the generator

c. feed the CLK from the same generator on J5 (set the desired frequency on the generator).

d. installed the ADS54Jxx 1.8 GUI and the HSDC Pro v5

I tried to use the prepared config files given the by the ADS54Jxx GUI by doing the following:

a. loaded the .cfg file for a given freq (e.g LMK_Config_Onboard_983p04_MSPS.cfg). the frequency of the CLK always matched the frequency given in the file name.

b. modified under PLL1 tab CLK1In buffer type to CMOS

c. under CLK outputs turned OFF under CLKOut 2&3  the DCLK (powerdown)

d. pressed reset button on the demo board (SW1)

e.  loaded the ADS54J60_LMF_8224.cfg

Then I started the HSDC (loaded the same FW as LMF_8224) and changed the ADC output data rate to the specific sampling frequency. And pressed "Capture".

Problem:

If I use the files and repeat the process above for the frequencies 1024,983.04 and 819.2 (and use the appropriate files as given by the GUI) all works fine.

As soon as I start using lower frequencies (491.52, 450.56, 409.6, 307.2, 245.76, 122.88) the acquisition doesn't work anymore. The error is as given the attachment.

In fact I can confirm the 2. is not satisfied since D4 is not blinking.

Any idea in which direction to look into?

Thank you for all your support,

Uros

 

  • 0
    TI__Guru* 91947 points

    Uros,

    The minimum serdes rate the ADC can operate per the data sheet is 2.5Gbps. Using a clock at 491.52MHz sets the serdes rate to 2.4576Gbps. The part may work at this rate but is not guaranteed.  Any sample rate lower than this will have a serdes rate lower than the minimum allowed.

    Jim 

  • 0 in reply to jim s
    Intellectual 280 points

    HI Jim,

     Yes, thank you this was the right direction but unfortunately did not completely solve the issue.

    I loaded the file for 4244.cfg which according to the datasheet should take me down to 250MSPS but it works with 409.6 MSPS but doesnt work with 307.2MSPS. I tried also with the 4211.cfg and I have smae issues.

    Sorry I clicked the problem is resolved (accidentally) but it isnt really. 

    Thank you,

    Uros

  • 0 in reply to Gruffalo
    TI__Guru* 91947 points

    Uros,

    In both cases, the LMK setting is incorrect for CLKout 0. The LMK config file sets this to 32 but it needs to be 8. This should fix your issue.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 280 points

    Hi Jim,

     Unfortunately works sporadically. I managed to get the 307.2 M .cfg work once and I can not repeat it anymore. The 245.76M never (OK there is the issue with the SERDES as you say). 

    Uros

  • 0 in reply to Gruffalo
    TI__Guru* 91947 points

    LMK_Config_Onboard_307p2_new_MSPS.cfgUros,

    Please try using the attached LMK config file for this frequency. Make sure both PLL lock LED's turn on after loading this LMK config file and make sure you have the 10MHz reference from the signal generator used to create the ADC clock connected to SMA J6.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 280 points

    Dear Jim,

     Yes the attached file helped and it works reliably. But unfortunately I can not see a difference between the "old" provided .cfg file (+ change in divider to 8 on CLK0 as you suggested) and the new file. What exactly is different in the new .cfg file?

    Thank you for your support.

    Uros 

  • 0 in reply to Gruffalo
    TI__Guru* 91947 points

    Uros,

    LMK04828 register 0x100 needs to be set to "8" for the correct FPGA clock divider.  The other change was register 0x150, bit 1 was set to zero to disable the hitless switch. I have notice in the past, when this is enabled (by default in the original configuration file), the PLL1 would not always lock. If you want more information regarding this, please check with the high speed clock group.

    Regards,

    Jim