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ADS1100: ADS1100

Part Number: ADS1100
Other Parts Discussed in Thread: ADS1110, DRV134, ADS1115

Hi team,

I am attaching the schematics of ADS1100A1IDBVT , please review it and let me know your inputs.
With regards,

Jayashree.

  • Jayashree,

    I don't have too many comments for the schematic. The ADS1100 is a moderately simple device and easy to use. The bypass capacitance is near 4.7uF, which is listed as the typical value from the datasheet. The input voltage divider is low enough to not be affected by the input impedance. The remaining pins are connected correctly.

    I did have two comments though:

    1. Make sure that GND and ANGND are connected directly. You don't want ground loops to affect the measurement.

    2. What is FB26? Sometimes there are inductors used to filter the supplies and small inductances shouldn't be a problem. However, large inductances can cause the supply to disrupt the operation of the ADC. The ADC will have digital currents, and with a large Ldi/dt, you can get large spikes in voltage. 


    Joseph Wu

  • Hi Joseph,

    Thanks for the reply.

    Joseph: The input voltage divider is low enough to not be affected by the input impedance. The remaining pins are connected correctly.

    Jayashree: What do you mean by this? Could you explain it to me in detail?

    Joseph: 1. Make sure that GND and ANGND are connected directly. You don't want ground loops to affect the measurement.

    Jayashree: I am connecting GND and ANGND through a ferrite bead, is that Ok? Attached image for your reference.

    Joseph: 2. What is FB26? Sometimes there are inductors used to filter the supplies and small inductances shouldn't be a problem.

    Jayashree: Fb26 I am using for as a filter circuit for the ADC IC supply power.

     

    With regards,

    Jayashree.

     

  • Jayashree,



    1. The input impedance of the ADC is not infinite, so whenever you are making a measurement, you are loading whatever you are measuring with the input impedance of the ADC. If you look in the electrical characteristics table, you'll see the input impedance:



    If you use PGA=1, the input impedance is 2.4MΩ. Because of this, the 5.1kΩ resistor looks like 5.089kΩ (as the two are equivalently in parallel). With such a low measurement resistor, this is a small error. If you were measuring a divider of 1.5MΩ and 510kΩ, then this input impedance would cause a much larger error.

    2. I would not use the ferrite bead connection between GND and ANGND, and use a direct short. Normally, we recommend using a continuous ground plane, and consider if there could be ground loops in the layout based on the placement of devices. Again, if you have large amounts of digital currents in the digital ground returning through to GND, then this could cause problems.

    3. If you are using a single ferrite bead for the supply, then I don't think it would be a problem. The ADS1110 in itself wouldn't be enough digital current to cause issues.



    Joseph Wu

  • Hi Joseph,

    1. I think the ferrite bead Fb26 is of less impedance (470ohm) it is actually given for the pie section filter should I still reduce it?

    2. FB12 ferrite bead is given for isolation of digital GND and Analog GND.

    I am attaching the schematics, please tell me whether I should make any changes in it.

    ADC review.pptx

  • Jayashree,

    My original comments still stand. I think the ferrite beads at the input of the supply should be fine, but I would not use ferrite beads to connect the analog and digital grounds.

    Joseph Wu

  • Hi Joseph,

    Got your point I have updated the schematics according, please go through it.

    In datasheet it is mentioned that 1 bit of resolution will be lost in single ended signals, could you explain it in detail.

    It is also mentioned to use Burr-Brown DRV134 balanced line driver. Does this means I should use DRV134 circuit also in my design to get accurate resolution.

    The sampling rate of this IC is 128 samples per second, can I have little more sample rate part with foot print compact to ADS1100

    With regards,

    Jayashree.

  • Jayashree,


    The reason that you lose one bit of resolution is because you're not measuring any negative signals. THe ADC measures the voltage difference between AINP and AINN. If AINN is higher than AINP, then your measurement is negative. With a PGA gain of 1, the input range is ±VDD and you use 16 bits to represent the inputs. With a single-ended measurement, AINN is tied to ground and the ADC won't measure negative signals (with the exception of a small negative offset if it exists). That means that there will only be positive values measured by the ADC, and you only use 15 bits to represent those numbers.

    In your setup, you measure a 30k/10k voltage divider. The voltage divider would be loaded by the DRV134. You would get errors because of this, and it's not worth the error to get the resolution.

    If you are interested in a faster data rate, the ADS1115 is a similar part and has a smaller footprint. I would note that the ADS1115 has an accurate internal reference, and does not use the supply as the reference.


    Joseph Wu

  • Hi Joseph,

    Thanks for the input.

    The ADS1115 IC suggested by you seems to be fine. I am using the same IC.

    I have updated the schematics with ADS1115 IC and attaching the pdf for your review.

    Awaiting for your valuable input.

    With regards,

    Jayashree.

  • Jayashree,

    I only have a few comments, similar to the previous schematic. 

    I would reduce the bypass capacitance at the VDD supply pin for the ADS1115. For that device, the recommended bypass is 0.1uF. For your schematic, you could just remove C744. Again, I would normally use a single ground plane. If that doesn't work, you can tie ANGND to GND together through a short. As I mentioned in a previous post, I would not tie ANGND to GND through an inductor. I would also note that the ground for the ADS1115 is ANGND, while the measurements for ADCIN_2 and ADC_IN1 are referenced to GND. In general, I'd avoid any potential ground loop and have a common ground. It's not shown on the schematic, but I assume that you'll have pull-up resistors on SCL and SDA. 

    For your input measurements, I'm not sure what your expected full range is, but you may want to maximize the usable range by scaling the measurement. In particular, you can scale the VIN_12V voltage divider to maximize the measured signal. For example, if you know that VIN_12V is going to be a maximum of 13V, you can scale the ADC to measure near 2.048V when the input is at max. Here you could use a 6kΩ / 33kΩ divider. With this divider, you would get 2V out of 2.048V when the VIN_12V is at 13V. This would maximize the input range of the measurement.

    Joseph Wu 

  • Hi Joseph,

    Sorry for the late reply.

    I have updated schematics according to your input.

    Please check whether it is proper.

    ADC_ALT_GPIO4_IO00 is of 3.3V max will this voltage be able to control the pin? 

  • Jayashree,


    There is still a 4.7uF cap as bypass in your schematic. In the previous post, I mentioned we recommend 0.1uF. It looks like you now have a common ground for your schematic which is good. Again, you could scale the voltage divider for VIN_12V, but it is fine as it is.

    As for the remaining schematic, the ALERT pin is an output of the ADS1115, ADC_ALT_GPIO4_IO00 should not be driving it. Also, where are the pull ups for SDA and SCL going? If they are being pulled up only to 3.3V, this might be a problem. Because the ADS1115 is running off of 5V, the min level to be received as a high is 0.7VDD. With a VDD of 5V, this is 3.5V. If SDA and SCL are pulled up only to 3.3V, then the ADS1115 may not receive it. If the micro and the pullups are at 3.3V, you may need a voltage level shifter to bridge the voltage difference.


    Joseph Wu

  • Hi Joseph,

    I had made 4.7uF cap as DNP. Sorry for not attaching the voltage translator circuit in the previous comment. I had attached the schematics of voltage translator also.

    Please got through it.

    The input range that VBAT_12V will be having is 8-18V. 

    With regards,ADC new part review feedback updated.pdf

    Jayashree.

  • Jayashree,

    I think that looks ok. I had been wondering about the voltage level translator for the ADC.

    What are you measuring with ADC_IN2? Do you expect that the input could overvoltage? If so, you may want to limit the amount of current going into AIN2 with a series 1kΩ resistor (you could just use R827).

    Joseph Wu

  • Hi Joseph,

    Thanks for your reply,

    I am measuring the voltage from an external source that would range from 0-5V at ADC_IN2 end.

    The will update the value of R827 with 1K.

    Do you have any other concerns in the circuit?

    With regards,

    Jayashree.

  • Jayashree,

    I would point out that right now R832 and R833 are listed as DNP. I assume that the microprocessor side has pull-ups. Regardless, you will need pull-ups for the I2C communication. 

    Other than that, I don't see any other issues with the schematic.

    Joseph Wu

  • Hi Joseph,

    The pull ups are given at the processor end already, in schematics R832 and R833 are given as extra options only.

    Thanks for your reply.

    With regards,

    Jayashree.