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ADS1282: Idle tones pushed, but not out of the passband.

Part Number: ADS1282

Hello,

I’m testing a custom PCB with an ADS1282 that I did which is plugged to the ADS1282EVM motherboard. My PCB replaces the ADS1282EVM daughter board equipping the ADC. I first tested it without the resistors at CAPP and CAPN to push the idle tones out of the passband. (ADS1282 Datasheet, section 9 and applications information). Indeed, I found some tones that looked like idle at frequencies 3.2Hz and a few harmonics.

I later added the two 75kΩ ±0.1% resistors between CAP and Ref as suggested in the application information. The tones disappeared but a new one arose at 1461Hz.

Red plot: without offset-inducing 75kΩ ±0.1% external resistors.

Blue plot: with offset-inducing 75kΩ ±0.1% external resistors.

I’m using the internally shorted (400Ω) input channel in the plots to show the problem doesn’t come from my input stage or connections. Nonetheless, the same behavior is repeated when I use Ch1 or Ch2 short circuited externally.

When exploring the blue signal in the time domain the 20mV offset is there.

The 1461Hz peak disappears when injecting a signal using a precision function generator.

I tested with PGA=1 and PGA=64. I only found this peak with PGA=1.

I have two units of this PCB and just one of them exhibits this peak at 1461Hz. The other one also showed idle tones and they just disappeared after adding the offset resistors, with no other peak appearing in return.

Do you know where this peak may be coming from?

Would you have any suggestion on how to make it go away? Just decreasing the 75kΩ ±0.1% resistors to 50kΩ ±0.1% maybe?

Could it be the symptom of a malfunction somewhere else?

  • Hi Martí,

    The Delta-Sigma modulator tone frequency is a function of the input offset voltage; as you change the input offset, the tone will shift to a new frequency. For very small input signals (or offsets) less than 20mV / PGA, the tone frequency will occur at a lower frequency and may appear in the digital filter pass-band depending on which data rate and filter you are using.

    As you increase the input offset (through the CAPP/N pins), the signal amplitude, or PGA gain the idle tone will be pushed out to a higher frequency and get attenuated by the digital filter. Therefore, changing any one of those parameters should help to remove the idle tone. Additionally, using a lower data rate will decrease the pass-band bandwidth and also reduce the range of input signals which will result in an idle tone in the pass-band.

    Decreasing the 75kOhm resistors will serve to increase the input offset voltage and may help with removing the idle tone, especially since device-to-device there may  up to a +/-200 uV max (or +/- 50 uV typical) variation in input offset voltage.

  • Thank you very much for your answer Chris,

    I'm sorry the plot I intended to attach didn't work. I try again:

    Red plot: without offset-inducing 75kΩ ±0.1% external resistors.

    Blue plot: with offset-inducing 75kΩ ±0.1% external resistors. No FIR. 32kSPS

    The offset (post-PGA) I generate is 20mV, as suggested in the datasheet’s application note, so the idle tones should be pushed to 6.7kHz or so (according to the datasheet, section 9.8 “Modulator”, which says that the idle tones are pushed by a ratio of 0.003V/kHz). When I examine the data without FIR filter I indeed find a peak close to 6.7kHz (6.3kHz in my case) but not only. I find other tones for which I have no explanation. The one bothering me, at 1462Hz, appeared right after I tried to push the idle tones out of the passband, so I deduce it is somehow related to idle tones, but I cannot say how. At least they seem to be something coming from the ADC.

    I wrote down the peaks frequencies and there are some funny coincidences when we study them. (Notice that I’m using a 4000kHz clock instead of a 4096kHz)

     

    Peaks Frequency (Hz)

     

    Peaks Distance (F(i+1)-F(i)) (Hz)

     

    Scaled to 4MHz

    Real freq (4000/4096)

     

    Scaled to 4MHz

    Real freq (4000/4096)

    F(1)

    1497.5

    1462.4

     

    1753.8

    1712.7

    F(2)

    3251.3

    3175.1

     

    1753.8

    1712.7

    F(3)

    5005.1

    4887.8

     

    1497.5

    1462.4

    F(4)

    6502.6

    6350.2

     

    1497.4

    1462.3

    F(5)

    8000

    7812.5

     

     

     

    Reformulating, the peak that bothers me, F(1), is at a frequency F(5) – F(4) which are probably the chopper frequency and the actual pushed idle tone frequency. Does it make any sense to you?

    Does this information give you any clue where these peaks might be coming from?

    Do you think this issue is worth looking into it closer, or I should just try to work it around by changing the offset? (even if we see I’m not dealing with regular idle tones.)

    If the rule I found (F(1) = F(5)-F(4)) is true, if I want F(1) out of the passband I should better try to decrease F(4) instead of increasing it, right? That is, replacing the 75k resistors by bigger ones instead of smaller.

    (fyi, I’m not in any rush to have answers)

    Kind regards,

    Martí

  • Hi Martí,

    If the observed tone is dependent on the input amplitude then my best guess it that it would either have to be a tone from the source generator or an idle tone of the modulator...

    It is possible for the idle tone to alias and reappear in the passband; Adding chopping into the equation, perhaps the tone is getting modulated by the chopping frequency and appearing at F(5) - F(4).

    Have you tried disabling chopping (i.e. setting the CHOP register bit to zero) to see if that also moves the tone frequency?

  • Thanks for your answer Chris,

    The plots I showed are obtained from Ch3 (ADC PGA inputs short circuited internally through 400Ω, MUX at 010). The 20mV (post-PGA) offset I talked about is the one induced by the 75kΩ ±0.1% resistors between CAPP & CAPN and REF+ & REF-. So there is no external source. I’m sorry my explanations may be a little confusing and not always complete, short, clear and unambiguous.

    I won’t be testing new configurations for a few days as I have another issue to attend, so the test without chopper will wait.

    As I told in the first post, I have two units of the same PCB working and only one of them has this 1462Hz peak.

    • The PCB version with the problem has lighter PS decoupling next to the ADC (after the LDOs). I tried to reduce it to see how low I could go without issues, to test a worst case. Does the kind of behavior I’m experimenting, in your opinion, look like something that could be related to ADC poor PS decoupling?
    • The problem I see, in your opinion, is it something that looks “ADC unit dependent” or more “PCB layout and surrounding circuit dependent”?

    At some point I will test the other PCB (the one without the problem) without FIR to see if I also have more peaks than in figure 32 of the ADS1282 datasheet.

    Have a nice day,

    Martí

  • Hi Martí,

    Maybe power supply noise is factor, but I'd think that with an LDO and the delta-sigma ADC's inherently high PSRR that it likely wouldn't be an issue. When I have seen power supply noise appear in the FFT, it typically is a wide "lump" and not a single tone frequency.

    Do you have switching power supply in your system? Do you know what frequency it switches at and what the LDO's PSRR is at that frequency? Typically, you'd want to avoid using a switching power supply that switches at some multiple of the modulator sampling rate, since the ADC's digital filter response will be mirrored and have additional passbands regions around these frequencies. You're using a 4 MHz fCLK so the modulator sampling rate will be 1 MHz.

    Also note, we've observed that placing a decoupling capacitor between the ADS1282's AVDD and AVSS supplies can be more effective than decoupling each supply rail to ground.

    The tone frequency will be device dependent mainly because the offset error is also device dependent.

  • Hello,

    I did some more tests to try to find out where the peak that bothers me, at F(1), comes from. I generated spectra of all the following test cases:

    • FIR OFF, @32kSPS
    • Chopper ON & OFF
    • PGA gains 1, 4 & 64
    • ADC Mux @ Ch3 (PGA shorted internally through 400Ω)
    • 3 different hardware supports:
      • TI ADS1282EVM original PCB
      • Custom board (made by me) equipped with ADS1282 & pluggable to TI ADS1282EVM mother board.
        • V1: Without issues. Doesn’t show F(1) annoying peak.
        • V2: Does show F(1) peak

    Summarizing, with my custom board V2, Chopper ON, PGA=1 I had the following (I include the frequencies relationships I found, that might help explain where the tones come from):

     

    Peaks Frequency (Hz)

     

    Peaks Distance (F(i+1)-F(i)) (Hz)

    Who is this peak?

     

    Scaled to 4MHz

    Real freq (4000/4096)

     

    Scaled to 4MHz

    Real freq (4000/4096)

     

    F(1)

    1497.5

    1462.4

     

    1753.8

    1712.7

    F(1)=F(5)-F(4)

    F(2)

    3251.3

    3175.1

     

    1753.8

    1712.7

    2x F(2) = F(4)

    F(3)

    5005.1

    4887.8

     

    1497.5

    1462.4

    F(3) = F(4)-F(1)=2*F(4)-F(5)

    F(4)

    6502.6

    6350.2

     

    1497.4

    1462.3

    Main idle tone

    F(5)

    8000

    7812.5

     

     

     

    Chopper

     

    I won’t show all the test cases results as I think it would be too long and not that helpful. My main conclusions pulled from the tests are the following:

    • The TI ADS1282EVM original board doesn’t have the offset resistors (75kΩ, 20mV/PGA offset) so the test data obtained is of no use for my case study.
    • Peaks at F(1) and F(3) are only found in one of my PCBs, V2, and not in V1. The only difference between PCBs is that I removed some decoupling capacitors in AVSS and AVDD and replaced some ferrites by 0Ω before and after the LDOs generating the supply.
    • The relationships between peaks frequencies I describe in my table are met in all cases.
    • When chopper is OFF tone at F(5) is still there. I guess the chopper clock is still there for some other reason.
    • When Chopper is OFF the other tones are still there, but F(4) is slightly shifted. This effect increases as PGA increases. I interpret this effect as a consequence of PGA offset not being compensated anymore.
    • @PGA = 64 the idle tones seem lower or, some, not any longer there I understand they get flooded by the PGA input floor noise.

    The comment you make about eventual switching PS with a frequency close to a multiple of fMOD is interesting. Definitely, it is something I had in mind to be considered at a system level. However, in this case, all the tones I see are at frequencies that can be obtained with simple algebraic calculations using F(4) & F(5). I don’t think there is any other frequency source having an impact, as it would show up at a frequency somehow decorrelated from F(4) & F(5).

    At some point I will try to solder a decoupling capacitor at AVSS & AVDD (or between them) at my PCB V2, to check if these F(1) & F(3) tones remains or not. I cannot see any other reason explaining the behavior difference between my two PCBs, V1 & V2.

    Have a nice day