Part Number: ADS1248
We have an application where we have 5 ADS1248 connected to various sensors.
We ave 5 different CS, one common ADSTART and one common RESET, they are connected in parallell on the SPI-Bus
On each AD we have 2 RTDs connected and we are using the internal IDACs for excitating the sensors, current set for 1mA.
Now we are experiencing spurious "resets" on them, sometimes all of them, and sometimes some of them, as it seems that the IDAC0 and IDAC1 registers is overwritten, it also happens that only one of the IDACS is shut down, leaving the other IDAC operating normally.
Since they share the same HW-RESET, it cannot be a hardware reset, since all of them would have been reset simultainiously.
We have been searching both source-code and assembler output for any hint on what is happening, sofar we ended upp in nothing that coukd explain why they are selectivly reset.
Is there any condition in the actual chip that could cause an internal reset, like overloading IDACs etc (now, I cannot understand how to overload a current generator), or anything else that could cause this behaviour.
I apologize for the delayed response. This sounds like it could be a transient that is getting back through the IDAC and shutting the IDAC down. Do you have any input protection on the IDAC sources? Can you send me your schematic for review?
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In reply to Bob Benjamin:
Yes, I can do that, but to where
In reply to Tomas Larsson1:
You can zip up all files and information and attach to the post.
Or if you prefer you can send to the following email address:
Sent it through mail.
Schematically you have the correct idea on input protection, but with your implementation there can be the possibility of a transient producing a condition where the Absolute Maximum Ratings will be violated. The AN24 input appears to be ok, but for the IDACs and other inputs you can exceed the ratings of no greater than AVDD + 0.3V, AVSS - 0.3V and maximum current of 10mA.
Let's take one pin as an example. The IDAC output on the IEXC1 pin connects to net AN0REF+, and directly connects to a TVS array. The clamp voltage of the TVS array is typically 8.2V. The AVDD for the ADS1248 is 5V. The maximum voltage allowed on this pin is 5 + 0.3V, so the clamp voltage exceeds the maximum allowable by about 3V, and will most certainly exceed 10mA for any sustained transient. You do have a series resistor for current limit, but this will only limit current to protect the TVS array. There are several different approaches to protect both the TVS array and the ADS1248. The easiest is to split the series resistor now in place so that there is resistance for both devices.
Another approach is to add a Schottky diode so that current can only flow one direction from the IDAC. This is a good approach as is the resistor and it is possible to use both as long as the IDAC compliance voltage is met.
For the regular inputs, you would need to limit current into the ADS1248.
Hi Bob, thanks for the input, I will look into this in the upcomming revision of the card.
If it would solve the current problem, I don't know, since this problem just surfaced, we haven't seen it before, and we have been using this design for the past 7-8 years, or so.
Regardless, I wuld have to do things right anyway.
I am beeing more convinced that we have some sort of strange software issue, or a compiler glitch, causing this.
Currently we think that under some very rare (from a software running point) condions, we might have the CS-lines affected, could pe a pointer that goes haywire and Points to the CS-port of the processor instead of memory.
If it would be a HW--problem, I Think we would have seen it much earlier, despite of that, we need to correct the schematic.
Again, thanks for your input.
Based on your original description of the issue, it sounds to me like a transient. However, as you have mentioned it is quite possible that some corrupted or unintended communication has taken place. For example, if in some way the internal reference has been inadvertently turned off, the IDAC current will cease to flow even though the IDAC current routing and output values are still correct.
If you have changed PCB vendors or components suppliers, it could still be a hardware issue as sometimes even these minor changes can make something that was marginal much more pronounced.
One other thing we have noticed, in the datasheet, fig 81 timing diagram, there is pause between the RDATA command and the data read, this pause is not explained nor specified, how long should it be?
This separation in Figure 81 is for illustration only to delineate the command from the data. The RDATA command for the ADS1248 is actually decoded on the 7th SCLK edge and there is no additional setup time required.
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