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ADC128S102: Similar problem:ADC128S102QML-SP -- Dout are clocked out on the rising edges of the SCLK

Part Number: ADC128S102

Several months ago, I posited the question, "ADC128S102: something strange -- Dout are clocked out on the rising edges of the SCLK" 

We were using ADC128S102(CIMT) that time, and now we using ADC128S102QML-SP.

-- Frequencies for SCLK input is 8MHz~16MHz write in datasheet of ADC128S102,

-- Frequencies for SCLK input is 0.8MHz~16MHz write in datasheet of ADC128S102QML-SP.

We don't think this chip exists the frequency problem of  ADC128S102, So we still use 1.5625MHz for ADC128S102QML-SP, but now the same problem has arisen, and the phenomenon is exactly the same, so I don't need to repeat it.

I want to confirm whether the two chips have same structure, and we can only use 8MHz~16MHz for it?

Thanks,

Luddy

  • Hello,

    You are correct.

    These devices are part of the same family and share structures. The devices were released around the same time and used the same datasheet format. This is why the clock frequency spec is displayed as is

    Apologies for the continued confusion, but all the devices mentioned will work with clock frequency of 8Mhz to 16Mhz

    Regards

    Cynthia

  • Cynthia,

    I'm glad to receive your reply so soon, and help us confirm the frequeny range.

    We still haven’t find out when the abnormal phenomenon (Dout are clocked out on the rising edges of the SCLK)will happen. 

    We used many ADC128S102QML chips in one device. The abnormal phenomenon happens in some test conditions and doesn't happens in some others; it happens in some chips, some never.

    Can you explain that, when the chips working at a lower frequency, how the abnormal behavior occurs? What factors might cause it to happen by chance?

    Thanks,

    Luddy

  • Luddy,

    Unfortunately there is no characterization as to how the device will behave outside of the operational ranges.

    This devices is meant to function between 50kSPS to 1MSPS, this translates to the clock range between 8MHz to 16MHz.

    Consider anything outside of that to be outside of specified operating conditions. The device may continue to be operational below that range, but there is no way of knowing how the device will respond. The device will still be functional at low clock frequency but may show inconsistent and/or incorrect behavior

    Regards

    Cynthia

  • The datasheet of ADC128S102QML-SP states, fSAMPLE = 50 kSPS to 1 MSPS ,fSCLK = 0.8 MHz to 16 MHz. And I don't see the newer version or errata.

    Does this mean that the description in the datasheet is inaccurate?

    Also, there seem to be errors in section 6.8, tCSH/tCSS requirements, NOM value<MIN value. Similar confusion both exists in the datasheet of ADC128S102 and ADC128S102QML-SP.

    If these descriptions are indeed incorrect, can you give a formal revision or errata ?  These questions really confuse us, without knowing the cause.

    Thanks,

    Luddy

  • I agree that this method is very confusing and misleading, I have brought this up and we are looking into it

    To explain the t_CSH/t_CSS timing, the best practice is to have a 0s delay between the CS and SCLK, which is why it is listed as the nominal. But it is still function if this delay is up to 10ns. Again, this is very confusing and we are addressing it.

    Regards

    Cynthia