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ADS1282-SP: FSR Utilization, ENOB and Accuracy

Part Number: ADS1282-SP
Other Parts Discussed in Thread: ADS1278-SP, ADS1282

 Hello,

I have a couple of questions about how to interpert the datas from the ADS1282-SP, ENOB and Error Budget Analysis.

First of all, I have read all documentation on training.ti.com/adc-noise

I have read this presentation (btw, it's really help me to separate the type of errors introduced by the ADC).

In our design, we have a Vsignal_diff = 50mV going in differential into an ADS1282S-SP. This signal varies slowly in the time (DC signal).

From your table bellow, I should only consider (because i have a dc signal at the input of the ADC) : the Effective resolution, Noise-free resolution and Noise-Free counts to calculate the resolution i can achieved?

We have VREF=  VREP-VREFN = 5-0V = 5V. We plan to use only the SINC filter without the FIR filter at 128kSPS.

FSR =    VREF/PGA = 5/1 = 5V.

We can calculate the Resolution system:

Resolution Loss:

Log2(%Utilization) = log2(System FSR/ADC FSR) = log2 (50mV/5V) = 6.7bits

To calculate the Effective Resolution (bits), i don't know which SNR to take. The only SNR provided in the datasheet is for High Resolution at 4kSPS (see page 17). I tried to extrapolate (yellow values) the SNR to higher Sampling Rates and at diffirent PGA Gains. If I use the extrapolate values of the bellow table, I got a SNR equal to 102dB at 128kSPS at PGA =1.

  PGA (SNR Ratio dB)
SPS 1           64
250 130           114
500 127           111
1000 124           108
2000 121           106
4000 118           103
8000 115           100
16000 111           97
32000 108           94
64000 105           91
128000 102           88

FSR_rms = (VREFP-VREFN)/(2 x sqrt(2) x PGA) = 1.7677 Vrms (formula from the datasheet, if PGA = 1)

I can calculate the Vn,RMS =  FSR_rms / 10^(SNR/20) = 1.7677 / (10^(102 dB/20)) = 14.04uVrms (by using the extrapolate table above)

Effective Resolution = Log2(System FSR/Vn,RMS) =  Log2(50mV/14.04uVrms) = 11.79bits

System Resolution  = Effective Resolution-Resolution Loss = 11.79 - 6.7 = 5.1bits (This number represents the actual resolution which i can achieve in my system without considering errors like INL, Offset errors, Gain errors, Gain error drift and Offset error drift?)

However, if i  want to use a PGA equal to 64,

log2(System FSR x 64 / ADC FSR) = log2 (50mV x 64 /5V) = -0.644 bits

FSR_rms = (VREFP-VREFN)/(2 x sqrt(2) x PGA) = 0.02762 Vrms

Vn,RMS =  FSR_rms / 10^(SNR/20) = 0.02762V/ (10^(88 dB/20)) = 1.0996uVrms (88dB comes from the table above which i extrapolate)

Effective Resolution = Log2(System FSR/Vn,RMS) =  Log2(64 x 50mV/1.0996uVrms ) = 21.47 bits

System Resolution  = Effective Resolution-Resolution Loss = 21.47- 0.644bits = 20.82bits (This number represent the actual resolution which i can achieve in my system without considering errors like INL, Offset errors, Gain errors, Gain error drift and Offset error drift?)

 

If I'm taking the last case with a PGA = 64, my resolution system is 20.82bits. To calculate my error budget (INL, Offset Error, Drift, Gain Error, Gain error drift, Noise RTI), should I take 31 bits or 20.82 bits to calculate the ERROR in term of LSB?

If i'm taking 31 bits, 1 LSB voltage is 2.32nV and 0.000465 LSB (ppm) and i got these errors with a gain of 64, SNR = 88dB

  Source of Error VALUE ERROR (%) ERROR (LSB) ERROR (PPM) LSB (PPM)
DNL DNL 0 0.000 0.000 0.00 0
QUANTIZATION ERROR QUANTIZATION ERROR 0 0.000 0 0.00 0
NOISE RTI NOISE RTI (nVp-p) 3110.21 0.000062 1336 0.62 1336
INL INL (%FSR) 0.000001953 0.000001953 42 0.02 42
OFFSET Offset Error (uV) @PGA = 1, -38 38 0.049 1044536 486.40 1044536
Offset Drift (uV/Degrees) @PGA = 1, -0.01 0.01 0.001 16493 7.68 16493
GAIN Gain Error (%), -1.05 1.05 1.050 22548578 6720.00 14431090
Gain Error Drift (ppm/Degrees) @PGA=1, -1 1 0.004 82463 38.40 82463
  ERROR (%) ERROR (LSB) ERROR (PPM) LSB (PPM)
TOTAL ERROR (WCA) 1.38 29706402 10053 21588914
TOTAL ERROR (RSS) 1.09 23360054 7296 15668762
BITS LOSSES (WCA) 24.36      
BITS LOSSES (RSS) 23.90      

I'm loosing 23.90 bits on 31 bits. So, my system Resolution is 7.044 bits.

 

If i'm taking 20.82 bits (from the previous part), 1 LSB voltage is 2.701uV and 0.540 LSB (ppm) and i got these errors with a gain of 64, SNR = 88dB

  Source of Error VALUE ERROR (%) ERROR (LSB) ERROR (PPM) LSB (PPM)
DNL DNL 0 0.000 0.000 0.00 0
QUANTIZATION ERROR QUANTIZATION ERROR 0 0.000 0 0.00 0
NOISE RTI NOISE RTI (nVp-p) 3110.21 0.000062 1 0.62 1
INL INL (%FSR) 0.000001953 0.000001953 0 0.02 0
OFFSET Offset Error (uV) @PGA = 1, -38 38 0.049 900 486.40 900
Offset Drift (uV/Degrees) @PGA = 1, -0.01 0.01 0.001 14 7.68 14
GAIN Gain Error (%), -1.05 1.05 1.050 19437 6720.00 12440
Gain Error Drift (ppm/Degrees) @PGA=1, -1 1 0.004 71 38.40 71
ADC ERROR        
  ERROR (%) ERROR (LSB) ERROR (PPM) LSB (PPM)
TOTAL ERROR (WCA) 1.38 25607 10053 18610
TOTAL ERROR (RSS) 1.09 20137 7296 13507
BITS LOSSES (WCA) 14.18      
BITS LOSSES (RSS) 13.72      

I'm loosing 13.72 bits on 20.82bits. So my system resolution is 7.1bits. The resolution is 1LSB = VREF (5V) / 2^7.1bits = 0.0364V

Does-it make sense?

 

Thank for your help

 

  • For the first Table

     

     

  • Hello Jeremy,

    I am glad the ADC Noise training was helpful.  Please take a look at the Analog Engineer's Pocket Reference guide, which includes much of this information in a quick reference format.

    http://www.ti.com/lit/slyw038

    First, you state that you have an input signal of 50mV, and it is slow moving.  So yes, I would agree that the effective and noise free resolution is more applicable in your case.  ENOB takes into consideration AC signals, and includes the effects of harmonic distortion caused by the non-linearity in the ADC transfer curve. 

    I do have an assumption that your full scale signal swing is from 0V to 50mV.  If it is from -50mV to +50mV, then your effective full scale input signal range will be 100mV, which will change your calculations.  For example, if your input signal swing is 0V to 50mV, then your Resolution Loss calculation of 6.7b is correct.  However, if your input signal swing is -50mV to +50mV, then your Resolution loss would be log2 (100mV/5V) = 5.7bits.

    Regarding the SNR at the higher data rates using only the sinc5 filter, the best way to determine this is to measure the noise with shorted inputs on an evaluation board.  I would do this, but I do not currently have one available.  In any case, I think your estimates are not very far off since the noise is largely due to thermal noise, and each doubling of the data rate results in roughly a 2x increase in bandwidth, which results in a 3dB reduction in overall SNR. 

    20*log(SQRT(2))=3dB

    Also, when moving from 4ksps to 8ksps, you are also switching from the wideband FIR filter to just the sinc5 filter.  The -3dB bandwidth of the wideband filter is 0.413*Fdata, and the sinc5 filter is closer to 0.23*Fdata (see Figure 31 in the ADS1278-SP datasheet).  This will result in about 20*log(SQRT(0.413/0.23)) = 2.5dB higher SNR numbers.  However, your estimates are more conservative, and are still useful for your analysis.

    FSR_rms = (VREFP-VREFN)/(2 x sqrt(2) x PGA) = 1.7677 Vrms (formula from the datasheet, if PGA = 1)

    I can calculate the Vn,RMS =  FSR_rms / 10^(SNR/20) = 1.7677 / (10^(102 dB/20)) = 14.04uVrms (by using the extrapolate table above)

    Effective Resolution = Log2(System FSR/Vn,RMS) =  Log2(50mV/14.04uVrms) = 11.79bits


    I agree with your above calculations.  However, your effective resolution of 11.79bits is your system resolution since you have referred your noise to your input voltage range of 50mV.

    The ADC effective resolution is Log2(FSR/Vn,RMS) =  Log2(5V/14.04uVrms) = 18.44bs.  You can get back to your System resolution by subtracting the resolution loss from the ADC effective resolution; 18.4b-6.7b=11.7b.

    The same process applies with a PGA Gain=64.  The full scale input range of the ADC is now 5V/64=78.125mV, and your resolution loss will be log2(50mV/78.125mV)=-0.64b.

    Your calculation for FSR_rms is correct at 0.02762Vrms, and your input noise based on 88dB is also correct at 1.1uVrms.

    The effective resolution of your ADC is now based on the input noise relative to the FSR of 5V/64.

    Effective Resolution = Log2(ADC FSR/Vn,RMS) =  Log2(78.125mV/1.0996uVrms ) = 16.1b.

    Your system resolution relative to your full scale signal range of 50mV is now 16.1b-0.64b=15.47b.

    Based on the above calculations, you will get much better system resolution by using the PGA gain=64.  (15.47b vs 11.79b)

    Normally, when referring to Error terms relative to LSB, the LSB is based on the code that the ADC produces.  In the case of the ADS1282, this is a 32 bit word, so all values should be based on a 32b word size.  For example, the offset error of 50uV with PGA=1 and VREF=5V will be 50uV/5V=0.001%, or 10ppm of full scale range.  The LSB's would be 10e-6*2^32=42,950LSB.  This is a large number because of the word size, which is why LSB's are not commonly used for very high resolution ADC's.  

    Regarding your overall error analysis, for high accuracy systems, you would typically perform a system level calibration to eliminate the offset and gain errors.  At this point, your remaining errors will be due to noise, INL, and temperature related drift errors in gain and offset.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hello Keith,

    It's really appreciated your help and it makes sense for me.

    "Also, when moving from 4ksps to 8ksps, you are also switching from the wideband FIR filter to just the sinc5 filter.  The -3dB bandwidth of the wideband filter is 0.413*Fdata, and the sinc5 filter is closer to 0.23*Fdata (see Figure 31 in the ADS1278-SP datasheet).  This will result in about 20*log(SQRT(0.413/0.23)) = 2.5dB higher SNR numbers.  However, your estimates are more conservative, and are still useful for your analysis."

    It means in my analysis, I am more conservative than the reality? For example, instead of having a SNR = 102dB at 128kSPS, I have more chance to have a SNR = 105.5dB? The better way to know exactly is to measure directly on the board?

    To calculte the FSR Utilization, I can calculate in this way: 

    - PGA = 1, FSR Utilization (%) = 50mV/5V = 1%, (System FSR/ ADC FSR) . However if the signal swings -50mv to 50mV, it will be 100mV/5V = 3%

    - PGA = 64, FSR Utilization (%) = 50mV/0.078125V = 64% (better improvement by using the PGA set to 64.)

    "Based on the above calculations, you will get much better system resolution by using the PGA gain=64.  (15.47b vs 11.79b)"

    -If i'm choosing a gain of 64, i will get a system resolution system of 15.47bits. It means 1 LSB Voltage = 5V/2^15.47bits = 110.160uV. It represents the resolution I could get/achieve? 

    "The offset error of 50uV with PGA=1 and VREF=5V will be 50uV/5V=0.001%".

    - If I'm using a PGA = 64, the offset error will be = 50uV/(5/64) = 0.06%? 

    In the following bloc diagram and from my understanting, If i want to use the Calibration inside the ADC, I have to select the FIR filter (so reducing the SPS to the maximum of 4kSPS at the output)? Is-it possible to calibrate the ADC by using the commands (Offset and gains) if i want to use only the SINC filter?

    Thank you very much,

  • Hello Jeremy,

    It means in my analysis, I am more conservative than the reality? For example, instead of having a SNR = 102dB at 128kSPS, I have more chance to have a SNR = 105.5dB? The better way to know exactly is to measure directly on the board?


    Yes, your understanding is correct.  I am fairly certain this will be the case, but I have not looked at the SINC5 only filter on this device, which is why I suggest measuring to confirm.

    However if the signal swings -50mv to 50mV, it will be 100mV/5V = 3%


    Yes, but I think you have a typo; for an input signal swing of +/-50mV with a 5V reference, your FSR utilization will be 2%.

     PGA = 64, FSR Utilization (%) = 50mV/0.078125V = 64% (better improvement by using the PGA set to 64.

    Yes, with a gain of 64, the ADC input full scale range is now +/-2.5/64=+/-39mV, or FSR=0.078V.  FSR utilization is 50mV/78mV=64%.

    If i'm choosing a gain of 64, i will get a system resolution system of 15.47bits. It means 1 LSB Voltage = 5V/2^15.47bits = 110.160uV. It represents the resolution I could get/achieve? 

    Not quite; The system resolution of 15.47bits has been adjusted to a 50mV FSR input range.  1LSB in this case will be 50mV/2^15.47 = 1.1uV.

    If I'm using a PGA = 64, the offset error will be = 50uV/(5/64) = 0.06%?


    The offset error for the ADC core will be divided by the PGA gain, but there will be additional offset error in the PGA.  Voff=50uV is only valid for a PGA gain of 1.  Similar to the noise, the best way is to measure, but since we do not have data for offset at GAIN=64, we can estimate using the data in Figure 30 of the datasheet which does provide an offset for PGA=8.

    Voff (pga=1) = ~50uV.

    Voff (pga=8) = ~10uV.

    Voff ~=Voff-adc/PGA+Voff-amp

    50uV=Voff-adc/1+Voff-amp

    10uV=Voff-adc/8+Voff-amp

    Solving for Voff-adc=45.7uV and Voff-amp=4.3uV, then the estimated offset at PGA=64 will be around 5uV, or 5uV/5/64=0.006%.

    You are correct, the internal calibration registers only work with the FIR filter, not the sync filter.  This is not difficult to implement inside your processor.  After calculating the offset and gain correction factors, you would simply multiply the conversion result by the gain correction and then add the offset.

    There is a TI Precision Labs training that goes over how to do this in your system.

    https://training.ti.com/ti-precision-labs-adcs-understanding-and-calibrating-offset-and-gain-adc-systems?context=1139747-1140267-1128375-1139104-1134080

    Also, the output word can be either 24b or 32b.  When using 32b, the LSB is simply the sign bit of the result.  If you want to express the errors in LSB's, I would suggest you use the 24b word option, and scale your errors relative to this level.

    For VREF=5V, PGA=64 and a 24b word length, 1LSB=5V/64/2^24=4.66nV.

    Regards,
    Keith

  • Hello Keith,

    Thank you for all explanations and the detailed procedure for the offset. However, I'm confused because I have two different analysis and i don't know how I can correlate one with the other.

    - First analysis is to determine the System Resolution. Above, we have a system resolution of 15.47bits for a PGA = 64. From my understanding, this system resolution is ideal without considering offset, gain, DNL, and drits errors. Is-it correct?

    - Second analysis is to determine the errors introduced by the ADC itself : Gain, offset, INL, DNL, drift. This analysis is based on 1 LSB = 5V/64/2^24 or 1 LSB = 5V/64/2^32. First, how can we select to choose if the ouput word is 24b or 32 bits? I'm assuming it should be a SPI request for 24 bits or 32 bits?

    "Also, the output word can be either 24b or 32b.  When using 32b, the LSB is simply the sign bit of the result.  If you want to express the errors in LSB's, I would suggest you use the 24b word option, and scale your errors relative to this level." For VREF=5V, PGA=64 and a 24b word length, 1LSB=5V/64/2^24=4.66nV.

    In the previous message, we have 0.006% of error due to the offset with a PGA = 64.

    - How can I convert this error 0.006% in term of voltage? 

    - How can I corellate this error of 0.006% to the system resolution of 15.47bits? How can I applied the error from the second Analysis to the first analysis?

    Thank you,
    Jeremy

  • Hi Jeremy,

    I can help with your latest set of questions...

    Jeremy Chambon said:
    - First analysis is to determine the System Resolution. Above, we have a system resolution of 15.47bits for a PGA = 64. From my understanding, this system resolution is ideal without considering offset, gain, DNL, and drits errors. Is-it correct?

    Correct....Resolution, or noise performance, only deals with the "repeatability" of the ADC's measurement result. It doesn't not include any of the other error sources.

     

    Jeremy Chambon said:
    First, how can we select to choose if the ouput word is 24b or 32 bits? I'm assuming it should be a SPI request for 24 bits or 32 bits?

    Check this E2E FAQ regarding the ADS1282's output data format: https://e2e.ti.com/support/data-converters/f/73/t/650982

    You get a 30 or 31-bit word as a result, but you don't have to use all 30/31 bits. If noise and accuracy don't give you more than 24-bits, you can (if you want to) disregard the noisy bits, either by not clocking them out, or by right-shifting the data in software after you've read the result.

     

    Jeremy Chambon said:
    - How can I convert this error 0.006% in term of voltage? 

    The percentage is with respect to the ADC's FSR range so you can just multiply the FSR by 0.006%. Assuming FSR = 5V / 64V/V (i.e. with respect to the input of the PGA) the offset error at the input of the PGA is (5V/64) * (0.006/100) = 4.69uV

     

    Jeremy Chambon said:
    - How can I corellate this error of 0.006% to the system resolution of 15.47bits?

    A dynamic range of 15.47 bits means that the FSR is divided up into a total of 2^15.47 = 45,387.27 resolvable steps or (5V/64) / 45,387.27 = 1.7uV.

    0.006% is 0.006 parts in 100, or 1 part in 16,666.667, which is equivalent to 1 code step in LOG2(16,666.667) = 14.02 bits. (5V/64) / 16,667.667 = 4.69uV.

  • Hello Chris,

    Thank you for all informations. It's really appreciated.

    "Correct....Resolution, or noise performance, only deals with the "repeatability" of the ADC's measurement result. It doesn't not include any of the other error sources." So in a ideal world, if I would have a system resolution of 15.47 bits (by no considering any other error source), i could have a precision of 1.7uV per step...but we are not in a perfect world, so i should add or substract (offset could be postive or negative, i assume)  4.69uV to 1.7uV to determine what will be the final resolution of the ADC by taking account of the sources errors.

    -If we just consider the offset error (I'm assuming the idea will be the same for the gain error, noise, inl, error drit), 1 real resolution of the ADC could be 1.7uv+/-4.69uV= -2.99uV or 6.39uV? Does-it make sense?

    -How can i determine the accuracy of all of this?

    -From the analysis above, I have to use the PGA gain to 64. For the offset, we extrapolated the value with two points. However, In the datasheet of the ADS1282-SP (Page 14), I don't see the offset drift for a PGA =64.

    - Figure 22, The gain error chart is applicable for all PGA gains?

    -What represent the gain Match exactly, is-it a tolerance of the PGA gain itself? On the chart (figure 25), the gain match error is around 0.26%. So the PGA gain could vary to 1 +/- 0.26%?  Can I use 0.26% for also a PGA =64?

    Thank you both of you for answering to my questions,

    Jeremy

  • Hello Jeremy,

    The system resolution is based on the system noise and the input signal range.  This is not typically included in the accuracy calculation.  For accuracy, you could consider gain, offset, and non-linearity of the ADC.  In a very low resolution ADC, the resolution may in fact limit the accuracy, but in most high resolution ADC's, ADS1282 included, the noise is much lower than the gain, offset, and linearity errors.

    For system accuracy calculations, you can root-sum-square the errors, since these specifications have a statistical distribution.  Take a look at this TI Precision Lab that discusses this approach.

    https://training.ti.com/ti-precision-labs-adcs-statistics-behind-error-analysis?context=1139747-1140267-1128375-1139104-1128656

    We do not have specifications specifically for offset drift at PGA=64, same as offset.  However, Figure 23 provides specs for PGA=1 and PGA=8.  The same approach can be used for the offset drift as was done for offset to come up with an estimate.

    The Gain error will be different at different PGA settings.  In general, the system would be calibrated to eliminate the gain error, and then you would be left with gain drift, which is shown in Figure 24 for each of the PGA settings.

    There is a systematic gain error of about -1%.  The gain matching between units is the +/-0.3%.  However, if you calibrate, then this error is near zero, and you would be left with the gain drift.

    FYI, take a look at the DC specifications in the ADS1282 datasheet, not the ADS1282-SP.  The gain and offset values are mislabeled in the ADS1282-SP dataseheet.

    Regards,
    Keith

  • Hello Keith,

    Thank you for all clarifications.

    So to have the real System Resolution I need to considere the noise of the voltage reference, sensor, power supply noise,  front end circuitries and the ADC itself. I have watched a couple of TI presentation. And this one helps me a lot:

    I have almost the same circuits but I have some difference:

    - My sensor is a wheastone Bridge excited by a different source of excitaton compare to the voltage reference (Non-Ratiometric configuration)

    - I don't have any op amps in front en the ADC, only LPF

    - A voltage reference of 5V used for the ADC

    To calculate the SNR Total including (excitation circuit for the sensor, Sensor, Front end Circuitries and Voltage Reference), I have run a couple of simulations to compute the Total RMS Noise.

    1) From the datasheet and your help, I estimated the Total Voltage Noise of Vn_ADS1282 = 828 nVrms (SNR = 90.5dB, 128kSPS, PGA =64, VREF = 5)

    2) My voltage reference has a Total Voltage Noise of 465.36 nVrms

    3) My excitation circuit, sensor and LPF has a Total Voltage Noise of 2.74 uVrms (Output noise computed only the pin AINP)

    FSR Utilization = 9.53% with Fsrms = VREF/ (2*SQRT(2)*PGA) = 0.0276Vrms

    The Total RMS Voltage noise is Vn_Total = SQRT(828 nVrms^2 + (465.36 nVrms*FSR Utilization)^2 + (2.74 uVrms AINP)*FSR Utilization)^2  + (2.74 uVrms (AINN)*FSR Utilization)^2) = 9.0457e-07 Vrms. I can conclude on the SNR Total = 20 x LOG10(VFSrms/Vn_Total ) = 89.7 dB.

    I can now compute the System Effective Resolution = LOG2(ADC FSR/ Vn_total) = (5/64 /9.0457e-07 Vrms ) = 16.40bits

    My resolution loss is -3.39bits, I can deduce the System Resolution (by considering noise from Voltage reference, ADC itself, Excitation, sensor and signal conditioning)

    System Resolution =  16.40bits - 3.39bits = 13.01 bits.

    1)  Does the method makes sense?

    2) In this type of calculation, how can I introduce the noise fom the power supply?

    3) In the Total Voltage Noise , Should I consider the Voltage Noise on AINP and AINN or only one time on the input of the ADC (I'm using this ADC in truly differential mode)?

    In this presentation, https://training.ti.com/delta-sigma-adcs-voltage-reference

    The narrator said : Notice that using the internal reference results in the highest noise with respect to full scale range usage, while the ratiometric configuration is virtually equivalent to the ADC noise level alone."

    If i'm using a ratiometric topology (I use the same voltage reference for my excitation on the wheastone bridge and for the reference of the ADC) , it means i can remove the voltage noise from the Voltage Reference and from the excitation voltage inside the Total RMS Noise Voltage equation?

    The Total RMS Voltage noise is now Vn_Total = SQRT(Vn_ADC^2 + (VREF*FSR Utilization)^2 + {Vn_frond_end_without_excitation x 2  (AINP + AINP, Differential mode ) x FSR Utilization)}^2 )

    Thank you very much,
    Jeremy

  • Hi Jeremy,

    Everything looks good up to the total input noise calculation:

    The Total RMS Voltage noise is Vn_Total = SQRT(828 nVrms^2 + (465.36 nVrms*FSR Utilization)^2 + (2.74 uVrms AINP)*FSR Utilization)^2  + (2.74 uVrms (AINN)*FSR Utilization)^2) = 9.0457e-07 Vrms. I can conclude on the SNR Total = 20 x LOG10(VFSrms/Vn_Total ) = 89.7 dB.

    1. The ADC noise is referred to the inputs, before the gain of 64.
    2.  I assume you are also doing the same thing for the reference noise; Vref-noise/64=465nVrms.
    3.  Also, I assume you are calculating the excitation noise that is referred to the inputs of the ADC, at the output of your LP filter that connects directly to the ADC inputs.

    So, in this case, you would simply root-sum-square all of the noise sources together.

    Vn_Total = SQRT(828 nVrms^2 + 465.36 nVrms^2 + 2.74 uVrms^2  + 2.74 uVrms^2) = 3.99uVrms

    SNR Total = 20 x LOG10(VFSrms/Vn_Total ) = 76.8 dB

    System Effective Resolution = LOG2(ADC FSR/ Vn_total) = (5/64 /3.99uVrms ) = 14.30bits

    Please note that the reduced SNR and Effective Resolution is primarily due to the noise in your sensor and excitation source, not the ADC or Reference.

    Regarding the FSR Utilization, you had earlier stated your input signal range was 50mV.  Using PGA=64, this is gained up to 3.2V to the ADC core inputs.  Relative to the Reference, your actual FSR Utilization is 3.2/5=64%.  Since this only helps the VREF noise, and it is already low relative to the other noise components, I just assumed it is 100%.  It will not make much difference in the total Noise calculation after you RSS all noise components together.

    The noise from your power supply connected to the ADC and Reference supply pins will be attenuated by the PSRR ratings of each of these devices.  However, power supply noise can couple into the inputs as well.  Typically, the goal is to filter the power supply noise to the point to where it contributes a negligible amount of additional noise to the system.  A good LDO can be used to not only regulate, but clean up this additional noise.  For the VREF and ADS1282, an LDO similar to the TPS7A4700 can do a good job.

    If i'm using a ratiometric topology (I use the same voltage reference for my excitation on the wheastone bridge and for the reference of the ADC) , it means i can remove the voltage noise from the Voltage Reference and from the excitation voltage inside the Total RMS Noise Voltage equation?


    Yes, that is correct.  You must balance the R and C values in the passive filter to make sure the attenuation over frequency is the same for both the positive and negative differential inputs, but assuming this is done correctly, you can eliminate the noise due to the ADC reference, as well as the external excitation source.  You will still have the noise of the sensor itself, plus any thermal noise in the input resistors, but in many cases, these will be much lower than the excitation source noise.

    You may want to take a look at this application note that discusses ratiometric measurements.  This covers a 4-wire RTD example, but the concepts are the same.

    http://www.ti.com/lit/an/sbaa201/sbaa201.pdf

    Regards,
    Keith

  • Hello Keith,

    Thank you for the help again.

    1) The ADC noise is referred to the inputs, before the gain of 64.

    In my case, I got 828nV for the Total Noise of the ADC by using : FSR_rms/(10^(SNR_ADC/20) with FSR_rms = VREF/(2*SQRT(2)*PGA) with VREF = 5V and PGA = 64, SNR_ADC = 90.5dB at 128kSPS. So it means i'm already included the Gain of 64 and not before.... So I need to multiply this value by 64 (828nVrms x 64 = Vn_ADC )

    2) I assume you are also doing the same thing for the reference noise; Vref-noise/64=465nVrms.

    Actually, I obtained 465nVrms without considering the gain 64. My circuit is just a Voltage Reference with a low pass filter. I measured the Total RMS Noise after the LPF. So I should divide this Total RMS Noise by 64 as you said.

    3) Also, I assume you are calculating the excitation noise that is referred to the inputs of the ADC, at the output of your LP filter that connects directly to the ADC inputs. Correct, I simulated a Wheastone Bridge, and a LPF. I measured the Total RMS Noise after the LPF BUT before the PGA.

    I have seen in the presentation (https://training.ti.com/ti-precision-labs-adcs-calculating-total-noise-adc-systems) about the noise produced by the voltage reference and op-amps. The Total Noise RMS is simulated from 1Hz to 1MHz (voltage Reference and OP-amp (1Hz to 100MHz). However, the Total Noise RMS is frequency dependant. The selection of the maximum frequency should be selected in function of the frequency of the input signal and the frequency of samples of the ADC?

     

    Thank you, 

  • Hello Jeremy,

    For the Reference input, the bandwidth of the digital filter can be used as an estimate of REF noise bandwidth.  In your case, Fdata=128ksps, and the -3dB corner for the SINC5 filter is 0.23*Fdata, so F3db=0.23*128k=29.4kHz.

    For the input, you have an external filter.  If the -3dB frequency is less than 29kHz, use that as the bandwidth.  If not, then use the digital filter of 29.4kHz.  Keep in mind these are first order estimates, but a good place to start in estimating total system noise.

    Regards,
    Keith

  • Hello Keith,

    Thank you for your reply.

    Could you confirm this point bellow?

    In my case, I got 828nV for the Total Noise of the ADC by using this formula from the datasheet : FSR_rms/(10^(SNR_ADC/20) with FSR_rms = VREF/(2*SQRT(2)*PGA) with VREF = 5V and PGA = 64, SNR_ADC = 90.5dB at 128kSPS.

    You said: "1) The ADC noise is referred to the inputs, before the gain of 64."

    So it means i'm already included the Gain of 64 and not before.... So I need to multiply this value by 64 ? (828nVrms x 64 = Vn_ADC_referred to the inputs )

    Thank you very much,

  • Hi Jeremy,

    The SNR is relative to the full scale range.  If you refer noise to the ADC input pins, then using VREF=5V and PGA=64, your full scale input range is 00276Vrms, and the internal thermal noise of the ADC at these inputs is 828nVrms.  This results in an SNR of 90.5dB, (20*log(0.0276/828e-9).

    If you refer to the full scale input at the ADC core (internal to the ADC), then the SNR will still be the same.

    Noise referred to the ADC internal inputs = 828nVrms*64=52.99uVrms

    Full scale input range at ADC internal inputs = 5V/2/2*SQRT(2)=1.768Vrms

    SNR=20*log(1.768/52.99e-6)=90.5dB.

    As long as you are consistent with the same point in your system where you define full scale input range and noise, then your SNR calculations will be the same.

    Regards,
    Keith

  • Keith,

                I am following up on this topic while Jeremy fights other fires.  Jim Apperley   514 771 1421 .

    I hope you can help me understand the specs from a time domain standpoint.  Since we are using the ADS1282-SP  in a snapshot mode with dc signals that are being multiplexed to the input.  As you will see below we only take one sample per channel (after settling).  In this case I do not see how the SNR ratio can be applied directly.

    We have 8 channels that must be sampled at a rate of 48Hz. However to ensure the signals are reasonably aligned for the control loop they needed to be sampled close to gather, giving an effective sample rate of 480Hz for each channel.  The effective multiplexing and ADC conversion rate is thus 3840 Samples per second into the ADC.  There is no correlation between signals so the ADC has to be synced to restart sampling every  0.26mS.

    From your datasheet it seems the FIR filters have a long settling time and to achieve the channel select rate we must use the SINC5 filters with 5 sample settling time. This results in an ADC conversion rate of >19200  samples per second.  So the ADC sample rate must be set to 32K samples per second or higher. 

    In this configuration the PGA cannot be chopped and 1/f noise will affect the signal. 

    My real question can be summarized in the time domain. Ignoring reference noise, what is the expected  ADC rms noise expected in LSB or uV RMS (with a 5V reference range and PGA of x64) for the different sample rates (32Ksps and above) with the SINC5 filter. Our inputs are dc. 

    I see this as equivalent to the number of LSB that can be accumulated in one single sample at different sample rates. 

    With SINC5 filter and a sample rate 32Ksps the number of bits accumulated from the modulator in the 5 SINC5 cycles  should give not better than 9 bits of ENOB.  Is this correct.  

    It would be worthwhile if you could indicate if the ADS1282-SP is appropriate for our intended mode of use.

    Thanks

    Jim Apperley

    Staff scientist 

    MDA 

    514 771 1421

     

                 

  • Hi Jim,

    James Apperley said:
    I hope you can help me understand the specs from a time domain standpoint.  Since we are using the ADS1282-SP  in a snapshot mode with dc signals that are being multiplexed to the input.  As you will see below we only take one sample per channel (after settling).  In this case I do not see how the SNR ratio can be applied directly.

    The signal-to-noise ratio (SNR) that is defined in the ADS1282-SP datasheet (see equation 1), is not a typical SNR involving a sine wave input. Instead the SNR values are measured with a DC input and the resulting DC (RMS) noise is compared to the ADC's (RMS) full-scale range.

    Therefore, you can convert all of the SNR values to their respective RMS noise amplitudes which is probably more useful from a time-domain perspective. I've provided this conversion result below.

     

    James Apperley said:

    We have 8 channels that must be sampled at a rate of 48Hz. However to ensure the signals are reasonably aligned for the control loop they needed to be sampled close to gather, giving an effective sample rate of 480Hz for each channel.  The effective multiplexing and ADC conversion rate is thus 3840 Samples per second into the ADC.  There is no correlation between signals so the ADC has to be synced to restart sampling every  0.26mS.

    From your datasheet it seems the FIR filters have a long settling time and to achieve the channel select rate we must use the SINC5 filters with 5 sample settling time. This results in an ADC conversion rate of >19200  samples per second.  So the ADC sample rate must be set to 32K samples per second or higher.

    In this configuration the PGA cannot be chopped and 1/f noise will affect the signal.

    Indeed, the FIR filters indeed have a very long settling time...Generally, multi-channel applications that use the ADS1282 would dedicate a single ADC for each channel and then synchronize all of the ADCs so that all channels are measured simultaneously.

    However, it sounds like you're considering the use of an external multiplexer and then running the ADC at a much higher data rate to achieve the required throughput. According to Table 21, you'd have to run the ADS1282 at the 32kSPS data rate (assuming a 4.096 MHz fCLK) which would result in a new conversion result every 236.3 mS (neglecting digital delays and any additional time required for the MUX to settle).

    The PGA chopping; however, shouldn't affect the conversion time so I'm not sure I understand why chopping would not be an option. This kind of chopping is not averaging two conversion results (i.e. further increasing the conversion time), it's a higher-frequency chopping inside the PGA but it does have the effect of lowering the input impedance of the PGA.

     

    James Apperley said:

    My real question can be summarized in the time domain. Ignoring reference noise, what is the expected  ADC rms noise expected in LSB or uV RMS (with a 5V reference range and PGA of x64) for the different sample rates (32Ksps and above) with the SINC5 filter. Our inputs are dc. 

    I see this as equivalent to the number of LSB that can be accumulated in one single sample at different sample rates. 

    With SINC5 filter and a sample rate 32Ksps the number of bits accumulated from the modulator in the 5 SINC5 cycles  should give not better than 9 bits of ENOB.  Is this correct.  

    Here is my calculation for input referred noise (in nVrms) as well as the effective resolution (which is a measure of DC performance...ENOB is technically an AC performance metric related to SNR and THD; however some literature uses "effective resolution" and "ENOB" synonymously).

     

     

    James Apperley said:
    It would be worthwhile if you could indicate if the ADS1282-SP is appropriate for our intended mode of use.

    Due the requirement of aligning all 8-channels in time, I would consider using the ADS1278-SP as it is an 8-channel, simultaneously sampled ADC. Using a simultaneous sample ADC will give you better alignment in the time domain than trying to run the ADS1282-SP at a faster data rate (and incurring more noise in the measurement as a result).

    The other option would be to use more than one (2-8x) ADS1282-SP IC's so that each ADC could run at a slower data rate; however, this likely is not as cost effective.